IP Library Granted Patent US 10,446,509
Granted Patent B2
US 10,446,509 · App. 16/039,652 · Granted Oct 15, 2019

Methods of forming and operating microelectronic devices including dummy chips

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Quick Facts
Patent No.
US 10,446,509
App. No.
16/039,652
Granted
Oct 15, 2019
Kind
B2
Abstract

A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

Claims (16)

1. A method of forming a microelectronic device, the method comprising:

forming active bump pads within a chip mounting area;

forming electrically isolated, inactive dummy pads outside the chip mounting area and within a peripheral area, the peripheral area being adjacent to and at least partially surrounding the chip mounting area;

placing active chips on at least some of the active bump pads; and

placing dummy chips on at least some of the electrically isolated, inactive dummy pads, the dummy chips being located only on the electrically isolated, inactive dummy pads within the peripheral area.

2. The method of claim 1 , further comprising forming a redistribution layer comprising a dielectric material and a metal material, wherein forming the active bump pads and the electrically isolated, inactive dummy pads comprises forming the active bump pads and the electrically isolated, inactive dummy pads over the redistribution layer.

3. The method of claim 2 , further comprising:

forming a molding compound over the active chips, the dummy chips, and the redistribution layer; and

removing an upper portion of the molding compound to expose upper surfaces of the active chips and the dummy chips.

4. The method of claim 2 , wherein:

forming the active bump pads comprises electrically connecting the active bump pads to circuitry of the redistribution layer; and

forming the electrically isolated, inactive dummy pads comprises at least partially surrounding the electrically isolated, inactive dummy pads with the dielectric material of the redistribution layer.

5. The method of claim 3 , wherein placing the dummy chips comprises reducing an exposed cross-sectional area of an upper surface of the redistribution layer prior to forming the molding compound.

6. The method of claim 2 , wherein forming the redistribution layer comprises forming an interposer without forming a through substrate via (TSV) substrate.

7. The method of claim 1 , wherein placing the active chips and the dummy chips comprises placing only one active chip on a respective active bump pad and placing only one dummy chip on a respective electrically isolated, inactive dummy pad.

8. The method of claim 1 , wherein placing the active chips and the dummy chips comprises positioning the active chips and the dummy chips with upper surfaces of each of the active chips and the dummy chips being generally coplanar with one another.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →