IP Library Granted Patent US 10,651,381
Granted Patent B2
US 10,651,381 · App. 16/040,515 · Granted May 12, 2020

Apparatuses including electrodes having a conductive barrier material and methods of forming same

Inventors: Swapnil A. Lengade (Boise, ID); John M. Meldrim (Boise, ID); Andrea Gotti (Pozzo D'Adda, IT)
Assignee: Micron Technology, Inc.
H01L45/1608H01L27/2427H01L27/2463H01L45/06H01L45/12H01L45/1233H01L45/1246H01L45/1253H01L45/141H01L45/144
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Quick Facts
Patent No.
US 10,651,381
App. No.
16/040,515
Granted
May 12, 2020
Kind
B2
Abstract

Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, a second electrode portion is coupled to the second chalcogenide structure, and a third electrode portion is between the first and second electrode portions. A first portion of an electrically conductive barrier material is disposed between the first and third electrode portions. A second portion of the electrically conductive barrier material is disposed between the second and third electrode portions.

Claims (24)

1. An apparatus, comprising:

a first chalcogenide structure;

a second chalcogenide structure;

a plurality of electrode portions disposed between the first chalcogenide structure and the second chalcogenide structure;

electrically conductive barrier material disposed among the plurality of electrode portions, the electrically conductive barrier material comprising portions interspersed between one electrode portion and another electrode portion of the plurality of electrode portions, wherein a first electrode portion of the plurality of electrode portions is coupled to the first chalcogenide structure, and wherein a second electrode portion of the plurality of electrode portions is coupled to the second chalcogenide structure, and wherein at least one other electrode portion is disposed between the first and second electrode portions.

2. The apparatus of claim 1 , wherein the portions interspersed between the one electrode portion and the other electrode portion of the plurality of electrode portions comprises a first portion of the electrically conductive barrier material disposed between the first electrode portion and the at least one other electrode portion and a second portion of the electrically conductive barrier material disposed between the second electrode portion and the at least one other electrode portion.

3. The apparatus of claim 2 , wherein the at least one other electrode portion corresponds to a third electrode portion of the plurality of electrode portions, the plurality of electrode portions comprising three electrode portions.

4. The apparatus of claim 3 , wherein the first portion of the electrically conductive barrier material has a larger cross section than at least one of the first, second, and third electrode portions.

5. The apparatus of claim 1 , wherein the second chalcogenide structure is stacked together with the first chalcogenide structure, the plurality of electrode portions, and the electrically conductive material such that the apparatus has a substantially uniform cross section.

6. The apparatus of claim 1 , wherein both the first and second portion of the electrically conductive barrier material comprises at least one of titanium nitride, tungsten silicide, or silicon.

7. The apparatus of claim 1 , wherein the plurality of electrode portions comprise carbon.

8. The apparatus of claim 1 , wherein the plurality of electrode portions comprise an electrically conductive and thermally insulative material.

9. The apparatus of claim 1 , wherein the first chalcogenide structure comprises a switch and the second chalcogenide structure comprises a phase change memory storage element.

10. A memory cell, comprising:

a phase change device configured to store one or more bits of data; and

a switch integrally formed in the memory cell with the phase change device and electrically coupled thereto through an electrode;

wherein the electrode is separated by an electrically conductive barrier material that is discontinuous, the electrically conductive barrier material comprising a first portion and a second portion, wherein the electrode comprises a plurality of electrode portions disposed between the phase change device and the switch, the plurality of electrode portions interspersed among the first portion of the electrically conductive barrier material and the second portion of the electrically conductive barrier material, wherein a first electrode portion of the plurality of electrode portions is coupled to the switch, and wherein a second electrode portion of the plurality of electrode portions is coupled to the phase change device, and wherein at least one other electrode portion is disposed between the first and second electrode portion.

11. The memory cell of claim 10 , wherein the first portion is the same material as the second portion.

12. The memory cell of claim 10 , wherein the first portion is a different material from the second portion.

13. The memory cell of claim 10 , wherein the first electrode portion is formed in situ with the electrically conductive barrier material and the switch.

14. The memory cell of claim 10 , wherein a grain boundary of the first portion of the electrically conductive barrier material does not line up with a grain boundary of the phase change device.

15. The memory cell of claim 10 , wherein the switch comprises a chalcogenide switch.

16. The memory cell of claim 15 , wherein a grain boundary of the second portion of the electrically conductive barrier material does not line up with a grain boundary of the chalcogenide switch.

17. The memory cell of claim 10 , wherein the electrically conductive harder material is at least partially amorphous or at least partially crystalline.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2018
From: LENGADE, SWAPNIL A.; MELDRIM, JOHN M.; GOTTI, ANDREA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046409/0227 →