Elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor and methods of processing silicon nitride-comprising materials
View Patent ↗A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H 3 PO 4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H 3 PO 4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.
1. An elevationally-extending string of memory cells individually comprising a programmable charge storage transistor, comprising:
vertically-alternating tiers of insulative material and control gate material;
a channel pillar extending elevationally through multiple of the vertically-alternating tiers and comprising a projecting portion extending elevationally outward of the elevationally-outermost tier of control gate material;
tunnel insulator, programmable charge storage material, and control gate blocking insulator between the channel pillar and the control gate material of individual of the tiers of the control gate material; and
silicon nitride-comprising material encircling at least some of the projecting portion of the channel pillar, the encircling silicon nitride-comprising material comprising an elevationally-outermost portion and an elevationally-innermost portion, the elevationally-outermost portion having greater intrinsic mechanical stress in the tensile direction than does the elevationally-innermost portion, said intrinsic mechanical stress being variable elevationally through each of the elevationally-outermost portion and the elevationally-innermost portion.
2. An elevationally-extending string of memory cells individually comprising a programmable charge storage transistor, comprising:
vertically-alternating tiers of insulative material and control gate material;
a channel pillar extending elevationally through multiple of the vertically-alternating tiers and comprising a projecting portion extending elevationally outward of the elevationally-outermost tier of control gate material;
tunnel insulator, programmable charge storage material, and control gate blocking insulator between the channel pillar and the control gate material of individual of the tiers of the control gate material; and
silicon nitride-comprising material encircling at least some of the projecting portion of the channel pillar, the encircling silicon nitride-comprising material comprising an elevationally-outermost portion and an elevationally-innermost portion, the elevationally-outermost portion having greater intrinsic mechanical stress in the tensile direction than does the elevationally-innermost portion, difference in said intrinsic mechanical stress being along a stepped gradient, and comprising three steps in the stepped gradient between an elevationally-outermost surface of the elevationally-outermost portion to an elevationally-innermost surface of the elevationally-innermost portion.
3. An elevationally-extending string of memory cells individually comprising a programmable charge storage transistor, comprising:
vertically-alternating tiers of insulative material and control gate material;
a channel pillar extending elevationally through multiple of the vertically-alternating tiers and comprising a projecting portion extending elevationally outward of the elevationally-outermost tier of control gate material;
tunnel insulator, programmable charge storage material, and control gate blocking insulator between the channel pillar and the control gate material of individual of the tiers of the control gate material; and
silicon nitride-comprising material encircling at least some of the projecting portion of the channel pillar, the encircling silicon nitride-comprising material comprising an elevationally-outermost portion and an elevationally-innermost portion, the elevationally-outermost portion having greater intrinsic mechanical stress in the tensile direction than does the elevationally-innermost portion, difference in said intrinsic mechanical stress being along a linear gradient.
4. The string of memory cells of claim 3 wherein the linear gradient is straight.
5. The string of memory cells of claim 4 wherein the linear gradient is from an elevationally-outermost surface of the elevationally-outermost portion to an elevationally-innermost surface of the elevationally-innermost portion.
6. The string of memory cells of claim 3 wherein the linear gradient is curved.
7. The string of memory cells of claim 6 wherein the linear gradient is from an elevationally-outermost surface of the elevationally-outermost portion to an elevationally-innermost surface of the elevationally-innermost portion.
8. An elevationally-extending string of memory cells individually comprising a programmable charge storage transistor, comprising:
vertically-alternating tiers of insulative material and control gate material;
a channel pillar extending elevationally through multiple of the vertically-alternating tiers and comprising a projecting portion extending elevationally outward of the elevationally-outermost tier of control gate material;
tunnel insulator, programmable charge storage material, and control gate blocking insulator between the channel pillar and the control gate material of individual of the tiers of the control gate material; and
silicon nitride-comprising material encircling at least some of the projecting portion of the channel pillar, the encircling silicon nitride-comprising material comprising an elevationally-innermost portion comprising carbon, the encircling silicon nitride-comprising material comprising an elevationally-outermost portion having less carbon content, if any, than the elevationally-innermost portion, carbon being in the elevationally-outermost portion, said carbon content being variable elevationally through each of the elevationally-outermost portion and the elevationally-innermost portion.
9. An elevationally-extending string of memory cells individually comprising a programmable charge storage transistor, comprising:
vertically-alternating tiers of insulative material and control gate material;
a channel pillar extending elevationally through multiple of the vertically-alternating tiers and comprising a projecting portion extending elevationally outward of the elevationally-outermost tier of control gate material;
tunnel insulator, programmable charge storage material, and control gate blocking insulator between the channel pillar and the control gate material of individual of the tiers of the control gate material; and
silicon nitride-comprising material encircling at least some of the projecting portion of the channel pillar, the encircling silicon nitride-comprising material comprising an elevationally-innermost portion comprising carbon, the encircling silicon nitride-comprising material comprising an elevationally-outermost portion having less carbon content, if any, than the elevationally-innermost portion, difference in said carbon content being along a stepped gradient, and comprising three steps in the stepped gradient between an elevationally-outermost surface of the elevationally-outermost portion to an elevationally-innermost surface of the elevationally-innermost portion.
10. An elevationally-extending string of memory cells individually comprising a programmable charge storage transistor, comprising:
vertically-alternating tiers of insulative material and control gate material;
a channel pillar extending elevationally through multiple of the vertically-alternating tiers and comprising a projecting portion extending elevationally outward of the elevationally-outermost tier of control gate material;
tunnel insulator, programmable charge storage material, and control gate blocking insulator between the channel pillar and the control gate material of individual of the tiers of the control gate material; and
silicon nitride-comprising material encircling at least some of the projecting portion of the channel pillar, the encircling silicon nitride-comprising material comprising an elevationally-innermost portion comprising carbon, the encircling silicon nitride-comprising material comprising an elevationally-outermost portion having less carbon content, if any, than the elevationally-innermost portion, difference in said carbon content being along a linear gradient.
11. The string of memory cells of claim 10 wherein the linear gradient is straight.
12. The string of memory cells of claim 11 wherein the linear gradient is from an elevationally-outermost surface of the elevationally-outermost portion to an elevationally-innermost surface of the elevationally-innermost portion.
13. The string of memory cells of claim 10 wherein the linear gradient is curved.
14. The string of memory cells of claim 13 wherein the linear gradient is from an elevationally-outermost surface of the elevationally-outermost portion to an elevationally-innermost surface of the elevationally-innermost portion.