Method and apparatus for 3D capture synchronization

1. A method comprising:

receiving a first command via a first interface addressable via a first address; and

receiving a second different command via a second interface addressable via a second address, wherein the second address comprises a shared address, where the first interface and the second interface both are associated with a first peripheral device.

2. A method of claim 1 , further comprising:

receiving a clock signal at a clock input, wherein the first address is received responsive to the clock signal.

3. A method of claim 2 , wherein the clock input is separate from the first interface and the second interface.

4. A method of claim 1 , further comprising receiving via the first interface a unique address to replace the first address.

5. A method of claim 1 , wherein a second peripheral device is addressable via the shared address, where the first peripheral device and the second peripheral device are connected to a same bus, and where the second peripheral device is of a same or substantially same type as the first peripheral device.

6. A method of claim 1 further comprising:

storing an indication indicating whether the first peripheral device is an acknowledging peripheral device, and

where the first peripheral device is an acknowledging peripheral device, sending an acknowledge signal in response to a group command received via the second interface.

7. A method of claim 6 , wherein the group command is received at a same or substantially same time at least via the second interface associated with the first peripheral device and via a second peripheral device, of a same or substantially same type as the first peripheral device, connected to a same bus.

8. A method of claim 1 , wherein the first interface is configured to receive individual commands, and the second interface is configured to receive group commands.

9. A method of claim 1 , wherein the first interface and the second interface are camera control interfaces.

10. An apparatus comprising:

at least one processor; and

at least one non-transitory memory including computer program code;

the at least one non-transitory memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to perform:

receive a first command via a first interface addressable via a first address;

receive a second different command via a second interface addressable via a second address, where the first interface and the second interface both are associated with the apparatus; and

receive via the first interface a unique address to replace the first address.

11. The apparatus of claim 10 , wherein the apparatus is further caused to perform:

receive a clock signal at a clock input, wherein the first address is received responsive to the clock signal.

12. The apparatus of claim 11 , wherein the clock input is separate from the first interface and the second interface.

13. An apparatus comprising:

at least one processor; and

at least one non-transitory memory including computer program code;

the at least one non-transitory memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to perform:

receive a first command via a first interface addressable via a first address; and

receive a second different command via a second interface addressable via a second address, where the first interface and the second interface both are associated with the apparatus, wherein the second address comprises a shared address.

14. The apparatus of claim 13 , wherein a peripheral device is addressable via the shared address, where the apparatus and the peripheral device are connected to a same bus, and where the peripheral device is of a same or substantially same type as the apparatus.

15. The apparatus of claim 10 , wherein the apparatus is further caused to perform:

store an indication indicating whether the apparatus is an acknowledging peripheral device, and

where the apparatus is an acknowledging peripheral device, send an acknowledge signal in response to a group command received via the second interface.

16. The apparatus of claim 15 , wherein the group command is received at a same or substantially same time at least via the second interface associated with the apparatus and via a peripheral device, of a same or substantially same type as the apparatus, connected to a same bus.

17. An apparatus comprising:

at least one processor; and

at least one non-transitory memory including computer program code;

the at least one non-transitory memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to perform:

receive a first command via a first interface addressable via a first address; and

receive a second different command via a second interface addressable via a second address, where the first interface and the second interface both are associated with the apparatus, wherein the first interface is configured to receive individual commands, and the second interface is configured to receive group commands.

18. The apparatus of claim 10 , wherein the first interface and the second interface are camera control interfaces.

19. A system comprising:

a host device; and

at least two peripheral devices, where the at least two peripheral devices respectively comprise two different interfaces, the respective two different interfaces separately addressable via a respective different address using the host device, wherein one interface of the respective two different interfaces is separately addressable via a shared address.

20. The apparatus of claim 10 , wherein the apparatus comprises at least two camera modules.

21. The apparatus of claim 20 , wherein the individual commands and the group commands are configured to enable management of camera parameters of the at least two camera modules.

22. The apparatus of claim 21 , wherein the camera parameters comprise one or more of exposure parameters, autofocus parameters, or analog gain parameters.

23. A method comprising:

receiving a first command via a first interface addressable via a first address; and

receiving a second different command via a second interface addressable via a second address, wherein the second address comprises a shared address, where the first interface and the second interface both are associated with a first apparatus.

24. An electronic device comprising:

at least one processor; and

at least one non-transitory memory including computer program code;

the at least one non-transitory memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to perform:

enable an apparatus to:

receive a first command via a first interface addressable via a first address; and

receive a second different command via a second interface addressable via a second address, wherein the second address comprises a shared address, where the first interface and the second interface both are associated with the apparatus.

25. The apparatus of claim 14 , wherein the apparatus comprises the peripheral device.

26. A method comprising:

receiving a first command via a first interface addressable via a first address;

receiving a second different command via a second interface addressable via a second address, where the first interface and the second interface both are associated with a first peripheral device; and

receiving via the first interface a unique address to replace the first address.

27. A method comprising:

receiving a first command via a first interface addressable via a first address; and

receiving a second different command via a second interface addressable via a second address, where the first interface and the second interface both are associated with a first peripheral device, wherein the first interface is configured to receive individual commands, and the second interface is configured to receive group commands.