IP Library Granted Patent US 10,719,904
Granted Patent B2
US 10,719,904 · App. 16/043,978 · Granted Jul 21, 2020

Parallel processing apparatus and parallel processing method

Inventors: Taketoshi Yasumuro (Kawasaki, JP); Hirotaka Fukushima (Kawasaki, JP)
Assignee: FUJITSU LIMITED
G06T1/20G06F9/38
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Quick Facts
Patent No.
US 10,719,904
App. No.
16/043,978
Granted
Jul 21, 2020
Kind
B2
Abstract

A parallel processing apparatus includes, a plurality of operational circuits that execute operations for data in parallel, and a control circuit that, upon an end of operations for a first portion of the data, finds estimated operation time for operations for a second portion that is an object of operations subsequent to the first portion, based on target time for operational processing for the data and a data amount of remaining data for which no operation has been executed in the data, finds a second parallelism of the operations for the second portion, based on a first parallelism of the operations for the first portion, a measurement value of operation time for the operations for the first portion, and the estimated operation time, and causes operational circuits, numbering in a number indicated by the second parallelism among the plurality of operational circuits, to execute the operations for the second portion.

Claims (32)

1. A parallel processing apparatus comprising:

a plurality of operational circuits configured to execute operations for data in parallel, the data including at least a first portion and a second portion, the second portion of the data being an object of operations subsequent to the first portion of the data; and

a control circuit configured to execute a first processing upon an end of operations for the first portion of the data, the first processing including

obtaining estimated operation time for operations for the second portion of the data based on target time for operational processing for the data and a data amount of remaining data for which no operation has been executed in the data,

determining a second parallelism degree of the operations for the second portion of the data, based on a first parallelism degree of the operations for the first portion of the data, a measurement value of operation time for the operations for the first portion of the data, and the estimated operation time, the second portion of the data is a portion for which no operation has been executed, and

causing operational circuits, numbering in a number indicated by the second parallelism among the plurality of operational circuits, to execute the operations for the second portion,

the control circuit calculates a difference between predicted processing time for the operational processing for the first portion and actual processing time for the operational processing for the first portion, based on a measurement value of operation time for operations for a third portion that is an object of operations precedent to the first portion, a third parallelism of the operations for the third portion, the measurement value of the operation time for the operations for the first portion, and the first parallelism, and, when the difference exceeds a first threshold, decreases a data amount of the second portion below a data amount of the first portion.

2. The parallel processing apparatus according to claim 1 , wherein the control circuit determines the estimated operation time, so that processing time for the operational processing for the data is equal to or shorter than the target time and a difference between the processing time and the target time is smaller than a threshold, and repeats control in which the operational circuits numbering in the number indicated by the second parallelism are made to execute the operations for the second portion, with each of a plurality of portions of the data regarded as the first portion, until operations for a last portion are ended.

3. The parallel processing apparatus according to claim 1 , wherein, when the difference is below a second threshold that is below the first threshold, the control circuit increases the data amount of the second portion more than the data amount of the first portion.

4. The parallel processing apparatus according to claim 1 , wherein the control circuit finds the second parallelism, based on a product of a ratio of the measurement value of the operation time for the operations for the first portion to the estimated operation time and the first parallelism.

5. The parallel processing apparatus according to claim 1 , wherein the plurality of operational circuits are a plurality of logic operation circuits.

6. The parallel processing apparatus according to claim 1 , wherein the plurality of operational circuits are a plurality of processors.

7. A parallel processing method for parallel processing apparatus including a plurality of operational circuits that execute operations for data in parallel and a control circuit, the method comprising:

executing a first processing upon an end of operations for a first portion of the data, the data including at least a first portion and a second portion, the second portion of the data being an object of operations subsequent to the first portion of the data, the first processing being configured to:

obtain, by the control circuit, estimated operation time for operations for the second portion of the data based on target time for operational processing for the data and a data amount of remaining data for which no operation has been executed in the data;

determine, by the control circuit, a second parallelism degree of the operations for the second portion of the data, based on a first parallelism degree of the operations for the first portion of the data, a measurement value of operation time for the operations for the first portion of the data, and the estimated operation time, the second portion of the data is a portion for which no operation has been executed; and

cause, by the control circuit, operational circuits, numbering in a number indicated by the second parallelism among the plurality of operational circuits, to execute the operations for the second portion,

the control circuit calculates a difference between predicted processing time for the operational processing for the first portion and actual processing time for the operational processing for the first portion, based on a measurement value of operation time for operations for a third portion that is an object of operations precedent to the first portion, a third parallelism of the operations for the third portion, the measurement value of the operation time for the operations for the first portion, and the first parallelism, and, when the difference exceeds a first threshold, decreases a data amount of the second portion below a data amount of the first portion.

8. The parallel processing method according to claim 7 , comprising:

determining, by the control circuit, the estimated operation time, so that processing time for the operational processing for the data is equal to or shorter than the target time and a first difference between the processing time and the target time is smaller than a threshold; and

repeating, by the control circuit, control in which the operational circuits numbering in the number indicated by the second parallelism are made to execute the operations for the second portion, with each of a plurality of portions of the data regarded as the first portion, until operations for a last portion are ended.

9. The parallel processing method according to claim 8 , comprising increasing, by the control circuit, the data amount of the second portion more than the data amount of the first portion, when the second difference is below a second threshold that is below the first threshold.

10. A non-transitory computer-readable recording medium having stored a program that causes a parallel processing apparatus including a control circuit and a plurality of operational circuits to execute a process, the process comprising:

executing a first processing upon an end of operations for a first portion of the data, the data including at least a first portion and a second portion, the second portion of the data being an object of operations subsequent to the first portion of the data, the first processing being configured to:

obtain estimated operation time for operations for the second portion of the data based on target time for operational processing for the data and a data amount of remaining data for which no operation has been executed in the data;

determine, a second parallelism degree of the operations for the second portion of the data, based on a first parallelism degree of the operations for the first portion of the data, a measurement value of operation time for the operations for the first portion of the data, and the estimated operation time, the second portion of the data is a portion for which no operation has been executed; and

cause operational circuits, numbering in a number indicated by the second parallelism among the plurality of operational circuits, to execute the operations for the second portion,

the control circuit calculates a difference between predicted processing time for the operational processing for the first portion and actual processing time for the operational processing for the first portion, based on a measurement value of operation time for operations for a third portion that is an object of operations precedent to the first portion, a third parallelism of the operations for the third portion, the measurement value of the operation time for the operations for the first portion, and the first parallelism, and, when the difference exceeds a first threshold, decreases a data amount of the second portion below a data amount of the first portion.

11. The non-transitory computer-readable recording medium according to claim 10 , comprising:

determining, by the control circuit, the estimated operation time, so that processing time for the operational processing for the data is equal to or shorter than the target time and a difference between the processing time and the target time is smaller than a threshold; and

repeating, by the control circuit, control in which the operational circuits numbering in the number indicated by the second parallelism are made to execute the operations for the second portion, with each of a plurality of portions of the data regarded as the first portion, until operations for a last portion are ended.

12. The non-transitory computer-readable recording medium according to claim 10 , comprising when the difference is below a second threshold that is below the first threshold, increasing the data amount of the second portion more than the data amount of the first portion.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ORIGINAL COVER SHEET BY REMOVING PATENT NUMBER 10586039 PREVIOUSLY RECORDED ON REEL 69272 FRAME 546. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 1, 2025
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 070764/0091 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2024
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 069272/0546 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 24, 2018
From: YASUMURO, TAKETOSHI; FUKUSHIMA, HIROTAKA
To: FUJITSU LIMITED
Reel/Frame 046623/0615 →
Priority Claims (1)
JP 2017-149087 · Aug 1, 2017 · national
Continuity (1)
Related Publication 20190043157A1 · Feb 7, 2019
Cited By (6)
US 1,099,265 US 1,144,756 US 12,195,954 US 12,221,776 US 12,305,782 US 12,590,641