Apparatuses and methods for parallel I/O operations in a memory
View Patent ↗Apparatuses and methods for a multi-level communication architectures are disclosed herein. An example apparatus may include an input/output (I/O) circuit comprising a driver circuit configured to convert a first bitstream directed to a first memory device and a second bitstream directed to a second memory device into a single multilevel signal. The driver circuit is further configured to drive the multilevel signal onto a signal line coupled to the first memory device and to the second memory device using a driver configured to drive more than two voltages.
1. An apparatus, comprising:
an input/output (I/O) circuit comprising a driver circuit configured to convert a first signal directed to a first device and a second signal directed to a second device into a multilevel signal that includes more than two values, the driver circuit further configured to drive the multilevel signal onto a signal line coupled to the first device and to the second device.
2. The apparatus of claim 1 , wherein the driver circuit comprises a multi-leg driver that is divided into at least two sections for driving the more than two voltages.
3. The apparatus of claim 2 , wherein the driver circuit includes an encoder configured to provide a first control signal and a second control signal, wherein the driver circuit is configured to provide the multilevel signal in response to the first control signal and the second control signal.
4. The apparatus of claim 3 , wherein the first control signal is configured to control a first driver leg of the driver circuit and the second control signal is configured to control a second driver leg of the driver circuit.
5. The apparatus of claim 4 , wherein the first driver leg and second driver leg may each comprise more than one leg in parallel.
6. The apparatus of claim 4 , wherein the first driver leg provides a greater drive strength than the second driver leg, wherein drive strength is determined by voltage or current drive impedance.
7. The apparatus of claim 1 further comprising a receiver and decoder circuit configured to receive a second multilevel signal via a second signal line coupled to the first device and to the second device, wherein the receiver and decoder circuit is further configured to decode the second multilevel signal to provide a third signal from the first device and a fourth signal from the second device.
8. The apparatus of claim 7 , wherein the receiver and decoder circuit comprises a plurality of comparators, wherein a comparator of the plurality of comparators is configured to compare a signal level of the second multilevel signal with a reference level and to provide a comparison signal based on the comparison, wherein the decoded second multilevel signal to provide the third signal and the fourth signal is based at least in part on the comparison signal.
9. The apparatus of claim 8 , wherein the receiver and decoder circuit is further configured to decode the multilevel signal to provide the first signal and the second signal based on known latencies between respective requests to provide information included in the first signal and in the second signal.
10. An apparatus, comprising:
an interconnect configured to receive a first transmit signal from a first memory device and a second transmit signal from a second memory device and to combine the first transmit signal and the second transmit signal into a multilevel signal that includes more than two values and to provide the multilevel signal to a host over a signal line.
11. The apparatus of claim 10 , wherein the multilevel signal is a command signal or an address signal.
12. The apparatus of claim 10 , wherein the first memory device includes a first drive strength and the second memory device includes a second drive strength such that the multilevel signal is decodable.
13. The apparatus of claim 12 , wherein:
the first memory device includes a first driver circuit and is configured to drive a first subset of driver legs of the first driver circuit; and
the second memory includes a second driver circuit and is configured to drive a second subset of driver legs of the second driver circuit.
14. The apparatus of claim 13 , wherein a number of driver legs in the first subset of driver legs of the first driver circuit is greater than a number of driver legs in the second subset of driver legs of the second driver circuit.
15. The apparatus of claim 13 , wherein the first driver circuit is further configured to provide a strobe signal to provide transition timing for the multilevel signal.
16. The apparatus of claim 15 , wherein the second memory is configured to receive the strobe signal from the first memory device and wherein a second I/O circuit of the second memory is configured to control timing of symbol transitions for the second transmit signal in response to the strobe signal.
17. The apparatus of claim 10 , wherein:
the first memory comprises a first receiver and decoder circuit configured to receive a second multilevel signal via a second signal line and to decode the second multilevel signal to provide a third transmit signal; and
the second memory device comprises a second receiver and decoder circuit configured to receive the second multilevel signal via the second signal line and to decode the second multilevel signal to provide a fourth transmit signal.
18. The apparatus of claim 17 , wherein the first receiver and decoder circuit uses a single comparator to decode the second multilevel signal to provide the third transmit signal, and wherein the second receiver and decoder circuit uses a plurality of comparators to decode the second multilevel signal to provide the fourth transmit signal.
19. A method comprising:
receiving a multilevel signal provided from a host at a first device and at a second device via a signal line;
decoding the multilevel signal at the first device to retrieve a first signal; and
decoding the multilevel signal at the second device to retrieve a second signal.
20. The method of claim 19 , wherein decoding the multilevel signal to retrieve the first signal at the first device comprises retrieving a most significant bit portion of the multilevel signal to retrieve the first signal.
21. The method of claim 20 , wherein decoding the multilevel signal to retrieve the second signal at the second device comprises retrieving a least significant bit portion of the multilevel signal to retrieve the second signal.
22. The method of claim 20 further comprising determining, at the first device, to decode the most significant bit portion of the multilevel signal based on a configuration setting stored at the first device.
23. The method of claim 20 further comprising:
receiving a chip select signal at the first device from the host; and
determining, at the first device, to decode the most significant bit portion of the multilevel signal based on a value of the chip select signal.