Phase-based cyclic redundancy check verification for wireless communication

1. A method for detecting bit errors in data packets, the method comprising:

receiving, from a remote entity and via a wireless medium, a data packet at a wireless transceiver;

receiving, from a phase differentiator of the wireless transceiver, a soft phase value of a symbol of the data packet;

receiving, from a phase slicer of the wireless transceiver, a sliced phase value of the symbol of the data packet;

determining an error measurement for the symbol based on the soft phase value and the sliced phase value;

comparing the error measurement for the symbol to an error measurement threshold for detecting bit errors in the data packet; and

detecting a bit error in the data packet based on the error measurement for the symbol exceeding the error measurement threshold.

2. The method as recited in claim 1 , wherein the error measurement for the symbol of the data packet is determined by measuring a distance between the sliced phase value of the symbol and the soft phase value of the symbol.

3. The method as recited in claim 1 , further comprising:

incrementing a symbol error count for the data packet responsive to the error measurement exceeding the error measurement threshold; and

wherein the bit error in the data packet is detected responsive to the symbol error count exceeding a symbol error threshold for detecting bit errors in the data packet.

4. The method as recited in claim 1 , further comprising:

incrementing a symbol error count for the data packet responsive to the error measurement exceeding the error measurement threshold;

dividing the symbol error count for the data packet by a number of symbols in the data packet for which an error measurement is determined to provide a quotient value indicative of symbol errors for the data packet; and

wherein the bit error in the data packet is detected responsive to the quotient value exceeding a symbol error threshold for detecting bit errors in the data packet.

5. The method as recited in claim 4 , wherein:

the symbol error threshold for detecting a bit error in the data packet is a configurable threshold; or

the symbol error threshold for detecting bit errors in the data packet is an average-based threshold useful to detect the bit error in the data packet.

6. The method as recited in claim 1 , further comprising indicating the bit error in the data packet to a higher-level entity associated with the wireless transceiver.

7. The method as recited in claim 6 , wherein indicating the bit error comprises setting a bit associated with signal quality of the data packet.

8. The method as recited in claim 7 , further comprising:

performing a cyclic redundancy check (CRC) on the data packet;

determining that the data packet passes the CRC; and

indicating a CRC pass to the higher-level entity of the wireless transceiver.

9. The method as recited in claim 6 , wherein the bit error in the data packet is indicated to one of a host controller interface, a host control interface driver, a protocol stack, a profile associated with the wireless transceiver, or a service associated with the wireless transceiver.

10. A System-on-Chip (SoC) comprising:

a wireless communication controller configured to receive data packets;

a receive chain configured to process the data packets and comprising a phase differentiator circuit and a phase slicer circuit; and

a cyclic redundancy check (CRC) verifier implemented at least partially in hardware and configured to:

receive, from the phase differentiator circuit, a soft phase value of a symbol of a data packet;

receive, from the phase slicer circuit, a sliced phase value of the symbol of the data packet;

determine an error measurement for the symbol based on the soft phase value and the sliced phase value;

compare the error measurement for the symbol to an error measurement threshold for detecting bit errors in the data packet; and

detect a bit error in the data packet based on the error measurement for the symbol exceeding the error measurement threshold.

11. The SoC as recited in claim 10 , wherein the CRC verifier is further configured to measure a distance between the sliced phase value of the symbol and the soft phase value of the symbol to determine the error measurement for the symbol.

12. The SoC as recited in claim 10 , wherein the CRC verifier is further configured to:

increment a symbol error count for the data packet responsive to the error measurement exceeding the error measurement threshold; and

detect the bit error in the data packet responsive to the symbol error count exceeding a symbol error threshold for detecting bit errors in the data packet.

13. The SoC as recited in claim 10 , wherein the CRC verifier is further configured to:

increment a symbol error count for the data packet responsive to the error measurement exceeding the error measurement threshold;

divide the symbol error count for the data packet by a number of symbols in the data packet for which an error measurement is determined to provide a quotient value indicative of symbol errors for the data packet; and

detect the bit error in the data packet responsive to the quotient value exceeding a symbol error threshold for detecting bit errors in the data packet.

14. The SoC as recited in claim 10 , wherein the CRC verifier is further configured to indicate the bit error in the data packet to a higher-level entity associated with the wireless communication controller.

15. The SoC as recited in claim 14 , wherein the wireless communication controller is further configured to:

perform a CRC on the data packet;

determine that the data packet passes the CRC; and

indicate a CRC pass of the data packet to the higher-level entity associated with the wireless communication controller.

16. The SoC as recited in claim 10 , wherein the wireless communication controller is configured to communicate in accordance with an institute of Electrical and Electronics Engineer (IEEE) 802.15 standard or a Bluetooth Special Interest Group (SIG) specification.

17. A non-transitory computer-readable storage media comprising instructions that, responsive to execution by a hardware-based processor, implement a cyclic redundancy check (CRC) verifier to:

receive, from a phase differentiator of a wireless transceiver, a soft phase value of a symbol of a data packet, the data packet received via a wireless medium;

receive, from a phase slicer of the wireless transceiver, a sliced phase value of the symbol of the data packet;

determine an error measurement for the symbol based on the soft phase value and the sliced phase value;

compare the error measurement for the symbol to an error measurement threshold for detecting bit errors in the data packet; and

detect a bit error in the data packet based on the error measurement for the symbol exceeding the error measurement threshold.

18. The non-transitory computer-readable storage media as recited in claim 17 , wherein the CRC verifier is further implemented to measure a distance between the sliced phase value of the symbol and the soft phase value of the symbol to determine the error measurement for the symbol of the data packet.

19. The non-transitory computer-readable storage media as recited in claim 17 , wherein the CRC verifier is further implemented to: increment a symbol error count for the data packet responsive to the error measurement exceeding the error measurement threshold; and detect the bit error in the data packet responsive to the symbol error count exceeding a symbol error threshold for detecting bit errors in the data packet.

20. The non-transitory computer-readable storage media as recited in claim 19 , wherein the CRC verifier is further implemented to indicate the bit error in the data packet to a higher-level entity associated with the wireless transceiver.