Apparatuses and methods of reading memory cells
View Patent ↗A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage ( VTH ) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (V TH1 ) of the memory cell and determining whether the V TH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped V TH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (V TH2 ); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the V TH1 and the V TH2 .
1. A method comprising:
determining that a first electrical response of a memory cell is within an overlapped electrical response region;
ramping a bias on the memory cell based at least in part on the determination that the first electrical response is within the overlapped electrical response region;
determining a second electrical response of the memory cell after ramping the bias on the memory cell; and
determining a state of the memory cell based at least in part on the first electrical response and the second electrical response.
2. The method of claim 1 , further comprising:
ramping a second bias on the memory cell prior to determining the first electrical response.
3. The method of claim 1 , wherein the first electrical response is between a first state distribution and a second state distribution.
4. The method of claim 1 , further comprising:
comparing the first electrical response and the second electrical response, wherein the state of the memory cell is determined based at least in part on the comparison of the first electrical response and the second electrical response.
5. The method of claim 1 , wherein determining that the first electrical response of the memory cell is within the overlapped electrical response region comprises:
performing an initial bias ramp on the memory cell until a first threshold event.
6. The method of claim 1 , further comprising:
applying an error correction code (ECC) after determining that the first electrical response is within the overlapped electrical response region.
7. The method of claim 6 , further comprising:
refraining from a subsequent ramping of the bias based at least in part on applying the ECC.
8. The method of claim 1 , wherein ramping the bias comprises:
applying a write pulse to the memory cell.
9. An apparatus comprising:
a memory array comprising a memory cell;
a memory controller coupled to the memory array and configured to:
determine a first electrical response of the memory cell;
determine that the first electrical response is within an overlapped electrical response region;
ramp a bias on the memory cell based at least in part on the determination that the first electrical response is within the overlapped electrical response region;
determine a second electrical response of the memory cell in response to ramping the bias on the memory cell; and
determine a state of the memory cell based at least in part on the first electrical response and the second electrical response.
10. The apparatus of claim 9 , wherein determining the first electrical response is based at least in part on ramping an initial bias on the memory cell.
11. The apparatus of claim 9 , further comprising:
applying an error correction code (ECC) after determining that the first electrical response is within the overlapped electrical response region.
12. The apparatus of claim 9 , wherein ramping the bias comprises:
applying a reset pulse to the memory cell.