Memory controller, memory system including the same, and operation method thereof

1. A memory controller, comprising:

a command input unit suitable for receiving a write command, a read command, and a send command;

a command counting unit suitable for performing a counting operation in response to the write command to produce a counted data;

a first Error Correction Code (ECC) encoding unit suitable for performing a first ECC encoding onto a data that is read from a memory device in response to the read command to produce a first ECC encoded data;

a second ECC encoding unit suitable for performing a second ECC encoding onto the counted data in response to the send command to produce a second ECC encoded data; and

a data output unit suitable for combining the first ECC encoded data with the second ECC encoded data to output a read data.

2. The memory controller of claim 1 , wherein the first ECC encoding unit performs the first ECC encoding based on a first frequency, and the second ECC encoding unit performs the second ECC encoding based on a second frequency which is higher than the first frequency.

3. The memory controller of claim 1 , wherein the command counting unit generates the counted data by increasing a count when the write command is inputted, and decreasing the count when a data is written in the memory device in response to the write command.

4. The memory controller of claim 1 , wherein the write command is inputted based on the second ECC encoded data of the read data.

5. The memory controller of claim 1 , wherein the data output unit includes a latch suitable for storing the first ECC encoded data.

6. The memory controller of claim 5 , wherein the memory controller generates and outputs a valid signal, when the first ECC encoded data is stored in the latch.

7. The memory controller of claim 6 , wherein the send command is inputted based on the valid signal after the read command is inputted.

8. A memory system, comprising:

a memory device that includes a plurality of memory cells; and

a memory controller suitable for reading a data stored in the memory device in response to a read command and performing a first Error Correction Code (ECC) encoding onto the read data to produce a first ECC encoded data,

wherein the memory controller counts a write command to produce a counted data, performs a second ECC encoding onto the counted data in response to a send command to produce a second ECC encoded data, and outputs the first ECC encoded data and the second ECC encoded data as a read data.

9. The memory system of claim 8 , wherein the memory controller includes:

a first ECC encoding unit suitable for performing the first ECC encoding based on a first frequency; and

a second ECC encoding unit suitable for performing the second ECC encoding based on a second frequency which is higher than the first frequency.

10. The memory system of claim 9 , wherein the memory controller further includes:

a command counting unit suitable for generating the counted data by increasing a count when the write command is inputted as well as decreasing the count when a data is written in the memory device in response to the write command.

11. The memory system of claim 9 , wherein the memory controller further includes:

a latch suitable for storing the first ECC encoded data, and

the memory controller generates and outputs a valid signal when the first ECC encoded data is stored in the latch.

12. The memory system of claim 11 , wherein the send command is inputted based on the valid signal after the read command is inputted.

13. The memory system of claim 8 , wherein the write command is inputted based on the second ECC encoded data of the read data.

14. A method for operating a memory system including a memory device and a memory controller, comprising:

performing, by the memory controller, a counting operation in response to a write command to produce a counted data;

reading, by the memory controller, a data from the memory device in response to a read command;

performing, by the memory controller, a first Error Correction Code (ECC) encoding onto the read data to produce a first ECC encoded data;

performing, by the memory controller, a second ECC encoding onto the counted data in response to a send command to produce a second ECC encoded data; and

combining, by the memory controller, the first ECC encoded data with the second ECC encoded data to output a read data.

15. The method of claim 14 , wherein the first ECC encoding is performed based on a first frequency, and the second ECC encoding is performed based on a second frequency which is higher than the first frequency.

16. The method of claim 14 , wherein the performing of the counting operation includes:

increasing a count when the write command is inputted; and

decreasing the count when a data is written in the memory device in response to the write command.

17. The method of claim 14 , further comprising:

inputting the write command based on the second ECC encoded data of the read data.

18. The method of claim 14 , further comprising, after the performing of the first ECC encoding onto the read data:

storing the first ECC encoded data; and

generating and outputting a valid signal.

19. The method of claim 18 , further comprising:

inputting the send command based on the valid signal.

20. A memory system, comprising:

a memory device for storing data; and

a memory controller suitable for:

performing a first ECC encoding on a data transferred from the memory device, in response to a read command;

performing a second ECC encoding on a counted data regarding a write command, in response to a send command; and

combining results of the separately performed first and second ECC encodings to generate a read data.