Apparatuses and methods for charging a global access line prior to accessing a memory

1. An apparatus comprising:

a memory array including signal lines; and

a control logic circuit configured to charge at least one signal line of the memory array responsive to a pre-access command, the control logic circuit configured, responsive to the pre-access command, to control a voltage of the at least one signal line based partly on a temperature of the apparatus.

2. The apparatus of claim 1 , wherein the signal lines comprise access lines and data lines.

3. The apparatus of claim 1 , wherein the apparatus corresponds to a smart phone, tablet device, electronic device, memory device, memory system, or any combination thereof.

4. The apparatus of claim 1 , wherein temperature of the apparatus corresponds to a temperature range between 125 and −40 degrees Celsius.

5. An apparatus comprising:

a memory array including signal lines; and

a control logic circuit configured to charge at least one signal line of the memory array responsive to a pre-access command, the control logic circuit configured to control a voltage of the at least one signal line based partly on a temperature of the apparatus, wherein the control logic circuit is configured to provide control signals based on temperature evaluation feedback associated with a temperature measurement of the apparatus.

6. The apparatus of claim 5 , wherein the control signals comprise signals to adjust signal line voltages based on the temperature evaluation feedback.

7. The apparatus of claim 5 , further comprising:

voltage circuitry configured to charge the at least one signal line of the memory array to a ready-access voltage based on the control signals.

8. The apparatus of claim 7 , wherein the control signals comprise signals to enable the voltage circuitry to develop the ready-access voltage.

9. The apparatus of claim 7 , wherein the voltage generator is configured to reset the at least one signal line to a different voltage than the ready-access voltage.

10. The apparatus of claim 5 , wherein the control signals comprise signals to reset the at least one signal line of the memory array to an inactive voltage responsive to a post-access command.

11. The apparatus of claim 5 , wherein the control signals comprise signals to indicate that memory array is ready to receive an additional command.

12. The apparatus of claim 10 , wherein the additional command corresponds to another pre-access command.

13. The apparatus of claim 1 , wherein the control logic circuit is configured to provide control signals to access the memory array.

14. The apparatus of claim 1 , further comprising:

a data cache coupled to the memory array, wherein the control signals comprise signals to store read data into the data cache.

15. A method comprising:

responsive to a pre-access command:

providing a control signal that prepares a signal line of a memory for memory access; and

determining a voltage for the signal line based partly on a temperature of the memory; and

accessing the memory.

16. The method of claim 15 , further comprising:

evaluating temperature feedback to determine the temperature of the memory.

17. The method of claim 16 , wherein the evaluating the temperature feedback occurs during a first time period.

18. The method of claim 17 , wherein determining the voltage for the signal line based partly on the temperature of the memory occurs during the first time period.

19. The method of claim 17 , further comprising:

during a second time period, enabling a voltage generator to develop a ready-access voltage.

20. The method of claim 19 , further comprising:

during a third time period, charging the signal line of the memory to the ready-access voltage.