Trench structures for three-dimensional memory devices
The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.
1. A memory device comprising:
a substrate;
a plurality of wordlines extending along a first direction over the substrate, wherein the plurality of wordlines form a staircase structure in a first region;
a plurality of channels formed in a second region and through the plurality of wordlines, wherein the second region abuts the first region at a region boundary; and
an insulating slit formed in the first and second regions and along the first direction, wherein:
the insulating slit completely passes through the first and second regions and along the first direction;
a first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction; and
the first width increases gradually beginning at the region boundary and ending at an end structure of the insulating slit.
2. The memory device of claim 1 , wherein the first direction is parallel to a top surface of the substrate.
3. The memory device of claim 1 , wherein the second direction is horizontal and perpendicular to the first direction.
4. The memory device of claim 1 , wherein the first width is greater than the second width by about 10 nm to about 50 nm.
5. The memory device of claim 1 , wherein the second width is uniform along the first direction within the second region.
6. The memory device of claim 1 , wherein the end structure comprises a curved end structure.
7. The memory device of claim 6 , wherein the curved end structure comprises an arc-shaped structure.
8. The memory device of claim 6 , further comprising a plurality of contact structures formed in the first region, wherein each contact structure of the plurality of contact structures is electrically connected to at least one wordline of the plurality of wordlines, and respective portions of a contact structure of the plurality of contact structures and the curved end structure that are furthest away from the region boundary are separated in the first direction by about 0.5 μm to about 2 μm.
9. A memory device comprising:
a wordline staircase region extending along a first direction;
an array region abutting the wordline staircase region at a region boundary; and
a plurality of slit structures completely passing through the wordline staircase region and the array region, wherein each slit structure comprises first and second portions formed in the wordline staircase region and the array region respectively, and a width of the first portion gradually increases beginning at the region boundary and along the first direction.
10. The memory device of claim 9 , wherein the plurality of slit structures extend along the first direction and the width of the first portion is measured in a second direction that is horizontal and perpendicular to the first direction.
11. The memory device of claim 9 , wherein the width of the first portion is greater than a width of the second portion by about 10 nm to about 50 nm.
12. The memory device of claim 9 , wherein the width of the first portion gradually increases between the region boundary and an end structure of the first portion.
13. The memory device of claim 9 , wherein a slit structure of the plurality of slit structures comprises a curved end structure.
14. The memory device of claim 13 , wherein the curved end structure comprises an arc-shaped structure.
15. The memory device of claim 9 , wherein the width of the first portion is greater than a width of the second portion.
16. A memory device comprising:
first and second wordlines in a wordline staircase region, wherein the first and second wordlines extend along a first direction;
an array region abutting the wordline staircase region at a region boundary; and
a slit structure along the first direction and completely passing through the wordline staircase region and the array region, comprising:
a first portion comprising a first width formed in the wordline staircase region between the first and second wordlines, wherein the first width gradually increases beginning at the region boundary and along the first direction; and
a second portion comprising a second width formed in the array region, and the first and second widths are different.
17. The memory device of claim 16 , wherein the slit structure continuously extends along the first direction and the first and second widths are measured in a second direction perpendicular to the first direction.
18. The memory device of claim 16 , wherein the first width of the first portion is greater than the second width of the second portion by about 10 nm to about 50 nm.
19. The memory device of claim 16 , wherein the second width of the second portion is uniform along the first direction.
20. The memory device of claim 16 , wherein the end structure of first portion comprises a curved end structure.