Memory devices with multiple sets of latencies and methods for operating the same
Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.
1. A method of operating a memory device, comprising:
enabling at least one memory operation feature from a set including a plurality of memory operation features;
determining a count of the number of memory operation features that are enabled;
determining whether a dynamic voltage and frequency scaling (DVFS) core of the memory device is disabled or enabled;
if the DVFS core is enabled, then applying a set of latency values from a plurality of sets of latency values, wherein the applying comprises:
applying a first set of the plurality of sets of latency values when the count of the number of memory operation features that are enabled is equal to a first number; and
applying a second set of the plurality of sets of latency values different from the first set when the count of the number of memory operation features that are enabled is equal to a second number different from the first number; and
executing a read command or a write command for one or more cells of the memory device based at least in part on the applied set of latency values.
2. The method of claim 1 , wherein the more than one memory operation features comprises at least one of a byte mode feature, a read data bus inversion feature, a read data copy feature, a read link error correction feature, or any combination thereof.
3. The method of claim 1 , wherein the one or more memory operation features comprises three features, and wherein the plurality of sets of latency values comprises three sets of latency values.
4. The method of claim 1 , wherein each set of latency values of the plurality of sets of latency values includes a plurality of latency values that each correspond to a mode register setting from a plurality of mode register settings of the memory device.
5. The method of claim 1 , wherein each set of latency values of the plurality of sets of latency values includes a plurality of latency values that each correspond to a clock ratio from a plurality of clock ratios of the memory device.
6. The method of claim 1 , wherein the plurality of sets of latency values comprises a plurality of sets of read latency values.
7. The method of claim 1 , wherein the plurality of sets of latency values comprises a plurality of sets of write latency values.
8. The method of claim 1 , wherein the plurality of sets of latency values comprises a plurality of sets of write recovery times.
9. The method of claim 1 , further comprising:
identifying a lower limit for a clock signal and an upper limit for the clock signal;
determining a setting for a mode register from a plurality of mode registers of the memory device, wherein the setting for the mode register comprises a four-bit value; and
operating the memory device at a frequency that is not less than the lower limit for the clock signal nor greater than the upper limit for the clock signal irrespective of the setting for the mode register.
10. A memory device, comprising:
a memory array; and
control circuitry configured to:
enable at least one memory operation feature from a set including a plurality of memory operation features;
determine a count of the number of memory operation features that are enabled;
determine whether a dynamic voltage and frequency scaling (DVFS) core of the memory device is disabled or enabled;
if the DVFS core is enabled, then apply a set of latency values from a plurality of sets of latency values, wherein the applying is configured to:
apply a first set of the plurality of sets of latency values when the count of the number of memory operation features that are enabled is equal to a first number; and
apply a second set of the plurality of sets of latency values different from the first set when the count of the number of memory operation features that are enabled is equal to a second number different from the first number; and
execute a read command or a write command for one or more cells of the memory device based at least in part on the applied set of latency values.
11. The memory device of claim 10 , wherein the control circuitry is further configured to:
execute a read command or a write command for one or more cells of the memory array based at least in part on the set of latency values.
12. The memory device of claim 10 , wherein the control circuitry is further configured to:
identify a lower limit for a clock signal and an upper limit for the clock signal;
determine a setting for a mode register from a plurality of mode registers of the memory device, wherein the setting for the mode register comprises a four-bit value; and
operate the memory device at a frequency that is not less than the lower limit for the clock signal nor greater than the upper limit for the clock signal irrespective of the setting for the mode register.
13. The memory device of claim 10 , wherein the more than one memory operation features comprises at least one of a byte mode feature, a read data bus inversion feature, a read data copy feature, a read link error correction feature, or any combination thereof.
14. The memory device of claim 10 , wherein the memory array and the control circuitry are located on a single semiconductor die.
15. The memory device of claim 10 , wherein the memory array and the control circuitry are located on separate semiconductor dies.
16. The memory device of claim 15 , wherein the separate semiconductor dies are located on a single memory module.
17. The memory device of claim 10 , wherein each set of latency values of the plurality of sets of latency values includes a plurality of latency values that each correspond to a mode register setting from a plurality of mode register settings of the memory device.
18. The memory device of claim 10 wherein each set of latency values of the plurality of sets of latency values includes a plurality of latency values that each correspond to a clock ratio from a plurality of clock ratios of the memory device.
19. The memory device of claim 10 , wherein the plurality of sets of latency values comprises a plurality of sets of read latency values.
20. The memory device of claim 10 , wherein the plurality of sets of latency values comprises a plurality of sets of write latency values.
21. The memory device of claim 10 , wherein the plurality of sets of latency values comprises a plurality of sets of write recovery times.