Boosting channels of memory cells

1. A method of operating a memory, comprising:

isolating a channel of a first memory cell from a first data line and isolating a channel of a second memory cell from a second data line; and

while continuing to isolate the channel of the second memory cell from the second data line:

increasing a voltage level of an access line coupled to a control gate of the first memory cell and coupled to a control gate of the second memory cell while continuing to isolate the channel of the first memory cell from the first data line; and

further increasing the voltage level of the access line while connecting the channel of the first memory cell to the first data line.

2. The method of claim 1 , wherein the voltage level of the access line is increased to concurrently boost the channel of the first memory cell and the channel of the second memory.

3. The method of claim 2 , wherein the voltage level of the access line is further increased to discharge the boosted channel of the first memory cell.

4. The method of claim 3 , wherein further increasing the voltage level of the access line does not discharge the boosted channel of the second memory cell.

5. The method of claim 1 , and further comprising:

programming the first memory cell after further increasing the voltage level of the access line and while continuing to isolate the channel of the second memory cell from the second data line.

6. The method of claim 1 , and further comprising:

maintaining a first select transistor in an off state to isolate the channel of the first memory cell from the first data line; and

maintaining a second select transistor in an off state to isolate the channel of the second memory cell from the second data line.

7. The method of claim 6 , and further comprising:

causing the first select transistor to switch to an on state to connect the channel of the first memory cell to the first data line while the voltage level of the access line is further increased.

8. The method of claim 7 , wherein the first select transistor and the second select transistor are maintained in the off state by applying a first bias voltage to a control gate of the first select transistor and the second select transistor.

9. The method of claim 8 , wherein the first select transistor is caused to switch to the on state by applying a second bias voltage to the control gate of the first select transistor and the second select transistor.

10. The method of claim 9 , wherein the second bias voltage maintains the second select transistor in the off state.

11. The method of claim 1 , wherein the first memory cell is in a selected memory string, and wherein the second memory cell is in an unselected memory string.

12. A memory device, comprising:

a memory array having a plurality of memory blocks; and

a controller, wherein the controller is adapted to control memory cells in a selected memory block of the memory array by:

isolating a first channel of a first memory cell from a first data line;

isolating a second channel of a second memory cell from a second data line;

increasing a voltage level of an access line coupled to a control gate of the first memory cell and coupled to a control gate of the second memory cell while continuing to isolate the first channel and the second channel; and

further increasing the voltage level of the access line while connecting the first channel to the first data line and while continuing to isolate the second channel.

13. The memory device of claim 12 , wherein the memory device is a NAND architecture memory device.

14. The memory device of claim 12 , wherein the memory device is a three-dimensional (3D) NAND architecture memory device.

15. The memory device of claim 12 , wherein the controller is adapted to program the first memory cell after further increasing the voltage level of the access line and while continuing to isolate the second channel.

16. The memory device of claim 15 , wherein the controller is adapted to program the first memory cell by biasing the first data line with a program enable voltage while biasing the second data line with a program inhibit voltage.

17. The memory device of claim 12 , wherein the controller is adapted to increase the voltage level of the access line to concurrently boost the first channel and the second channel, and wherein the controller is adapted to further increase the voltage level of the access line to discharge the boosted first channel.

18. The memory device of claim 12 , wherein the controller is adapted to maintain first and second select gate drain (SGD) transistors in an off state to isolate the first channel and the second channel, and cause the first SGD transistor to switch to an on state to connect the first channel to the first data line while the voltage level of the access line is further increased.

19. A method of programming a memory cell of a non-volatile NAND architecture memory array, comprising:

isolating a first channel of a first memory cell in a selected memory string from a first data line;

isolating a second channel of a second memory cell in an unselected memory string from a second data line;

applying a first voltage level to an access line coupled to a control gate of the first memory cell and coupled to a control gate of the second memory cell while continuing to isolate the first channel and the second channel;

increasing the first voltage level to a second voltage level while connecting the first channel to the first data line and while continuing to isolate the second channel; and

programming the first memory cell after increasing the first voltage level while continuing to isolate the second channel.

20. The method of claim 19 , wherein programming the first memory cell further comprises:

biasing the first data line with a program enable voltage while biasing the second data line with a program inhibit voltage.