Packet generation in the data plane of a forwarding element

1. A data plane circuit for a hardware forwarding element comprising:

a data plane circuit comprising:

a packet generator configured with two or more programmed triggering events and configured with two or more packet formats, wherein at least two of the two or more packet formats convey different information, wherein in response to a particular triggering event, the packet generator is to generate a packet based on a particular packet format and wherein the particular triggering event is one of the two or more programmed triggering events and the particular packet format is one of the two or more packet formats and

at least one programmable packet processing pipeline to receive the generated packet prior to transmission of the generated packet, wherein the at least one programmable packet processing pipeline comprises one or more match-action units (MAU) programmed to process one or more packets according to match-action configurations.

2. The data plane circuit of claim 1 , wherein the particular triggering event comprises one or more of: a port down event, packet recirculation event, or a timer event.

3. The data plane circuit of claim 2 , wherein the port down event comprises a receipt of a signal indicating an egress port is down.

4. The data plane circuit of claim 2 , wherein the packet recirculation event comprises receipt of a recirculation packet recirculated from an egress port of the data plane circuit to an ingress port of the data plane circuit.

5. The data plane circuit of claim 2 , wherein the timer event comprises one or more of: a one shot timer or an expiration of a timer that recurs after a period of time.

6. The data plane circuit of claim 1 , wherein the particular packet format comprises:

a packet size, one or more packet fields, and one or more packet field values.

7. The data plane circuit of claim 6 , wherein a packet field value of the one or more packet field values comprises a destination address.

8. The data plane circuit of claim 7 , wherein the destination address comprises at least one of an open systems interconnection (OSI) model Layer 2 (L2) destination address or a Layer 3 (L3) destination address, wherein:

the L2 destination address is a media access control (MAC) address of a destination of the packet; and

the L3 destination address is an Internet protocol (IP) address of the destination of the packet.

9. The data plane circuit of claim 1 , wherein

the packet generator is configured with one or more configuration sets,

in response to a particular triggering event, the packet generator is to select a configuration set of the one or more configuration sets, and

the selected configuration set is to identify a number of packets to generate.

10. The data plane circuit of claim 9 , wherein the packet generator is to provide a generated packet to a programmable packet processing pipeline of the at least one programmable packet processing pipeline and in response to processing of the generated packet, the programmable packet processing pipeline is to perform an action of a match-action.

11. The data plane circuit of claim 9 , wherein the selected configuration set is to also to identify one or more of: a template to use to generate the packet, number of batches of the packet to generate, number of packets in a batch of the batches, inter packet gap, and/or jitter.

12. The data plane circuit of claim 1 , wherein the forwarding element is one of a switch and a router.

13. The data plane circuit of claim 1 , comprising:

a set of ingress ports to process packets received at the forwarding element and

a set of egress ports to process packets prior to transmission of packets from the forwarding element.

14. A method performed by a data plane circuit of a forwarding element, the method comprising:

at the data plane circuit:

receiving a configuration of two or more programmed triggering events;

receiving a configuration of two or more packet formats, wherein at least two of the two or more packet formats convey different information;

detecting a triggering event in the data plane circuit and

based on detection of a particular triggering event, generating a packet based on a particular packet format, wherein the particular triggering event is one of the two or more programmed triggering events and the particular packet format is one of the two or more packet formats.

15. The method of claim 14 , wherein the triggering event comprises one or more of: a port down event, packet recirculation event, or a timer event.

16. The method of claim 15 , wherein the port down event comprises a receipt of a signal indicating an egress port is down.

17. The method of claim 15 , wherein the packet recirculation event comprises receipt of a recirculation packet recirculated from an egress port of the data plane circuit to an ingress port of the data plane circuit.

18. The method of claim 15 , wherein the timer event comprises one or more of: a one shot timer or an expiration of a timer that recurs after a period of time.

19. The method of claim 14 , wherein the particular packet format comprises:

a packet size, one or more packet fields, and one or more packet field values.

20. The method of claim 19 , wherein a packet field value of the one or more packet field values comprises a destination address.

21. The method of claim 20 , wherein the destination address comprises at least one of an open systems interconnection (OSI) model Layer 2 (L2) destination address or a Layer 3 (L3) destination address, wherein:

the L2 destination address is a media access control (MAC) address of a destination of the packet; and

the L3 destination address is an Internet protocol (IP) address of the destination of the packet.

22. The method of claim 14 , comprising:

receiving a configuration of one or more configuration sets and

in response to a particular triggering event, selecting a configuration set of the one or more configuration sets, wherein the selected configuration set identifies a number of packets to generate.