Scan chain operation in sensing circuitry
View Patent ↗An apparatus can include an array of memory cells coupled to sensing circuitry. The sensing circuitry can include a sense amplifier and a compute component. The sensing circuitry is to receive a scan vector and perform a scan chain operation on the scan vector. The sensing circuitry is controlled to write the resulting scan vector to a second portion of the array of memory cells.
1. An apparatus, comprising:
an array of memory cells coupled to sensing circuitry including a sense amplifier and a compute component, wherein the sensing circuitry is controlled to:
receive a scan vector from a first portion of the array of memory cells;
perform a scan chain operation on the scan vector without activation of a scan_in pin or a scan_out pin to yield a resulting scan vector; and
write the resulting scan vector to a second portion of the array of memory cells.
2. The apparatus of claim 1 , further comprising a controller coupled to the sensing circuitry and configured to cause the resulting scan vector to be compared to an expected value vector.
3. The apparatus of claim 1 , further comprising a controller coupled to the sensing circuitry and configured to cause an exclusive—or (XOR) operation to be performed between the resulting scan vector and an expected value vector.
4. The apparatus of claim 1 , further comprising a controller coupled to the sensing circuitry and configured to cause a vector resulting from performance of an exclusive—or (XOR) operation to be combined with a global resultant vector.
5. The apparatus of claim 1 , further comprising a controller coupled to the sensing circuitry, the controller to provide a clock signal to toggle logic in response to the scan operation completing.
6. The apparatus of claim 1 , the sensing circuitry to initiate the scan chain operation on at least one of a rising edge of a clock signal received from a clock, a falling edge of a clock signal received from the clock, or combinations thereof.
7. The apparatus of claim 1 , wherein the sensing circuitry is controlled to receive the scan vector, perform the scan chain operation, write the resulting scan vector, or combinations thereof without accessing a processing resource associated with a host coupled to the array and the sensing circuitry.
8. The apparatus of claim 1 , further a first shift register and a second shift register, wherein the scan vector is written to the first shift register, and wherein the resulting scan vector is written to the second shift register.
9. A system, comprising:
a host;
a memory device coupled to the host and comprising an array of memory cells coupled to sensing circuitry, wherein the memory device is configured to:
receive a scan vector from a first portion of the array;
perform a scan chain operation on the scan vector to generate a resulting scan vector; and
write the resulting scan vector to a second portion of the array, and wherein the memory device is configured to:
receive the scan vector, perform the scan chain operation, write the resulting scan vector, or combinations thereof, without transferring data from the memory device to the host.
10. The system of claim 9 , wherein the memory device further comprises:
a first shift register to which the scan vector is written; and
a second shift register to which the resultant scan vector is written.
11. The system of claim 9 , wherein the memory device is configured to receive the scan vector and write the resultant scan vector without activation of a scan_in pin or a scan_out pin.
12. The system of claim 9 , wherein the memory device is further configured to break the scan vector into multiple portions responsive to a determination that the scan vector exceeds a threshold length.
13. A method, comprising:
receiving a scan chain vector from a first portion of a memory array;
storing the scan vector in sensing circuitry having a sense amplifier and a compute component;
performing a scan chain operation on the scan vector using the sensing circuitry;
transferring the resulting scan vector to a second portion of the memory array and, prior to receiving the scan chain vector, determining that the scan vector is longer than a threshold length;
splitting the scan vector into a first portion and a second portion;
receiving the first portion of the scan chain vector;
performing the scan chain operation on the first portion of the scan chain vector;
receiving the second portion of the scan chain vector; and
performing the scan chain operation on the second portion of the scan chain vector.
14. The method of claim 13 , further comprising comparing the resultant scan vector to an expected output scan vector.
15. The method of claim 13 , comprising generating an indication that a scan test is successful in response to a determination that the resultant scan vector and an expected output scan vector have greater than a threshold number of data values in common.
16. An apparatus, comprising:
an array of memory cells coupled to sensing circuitry including a sense amplifier and a compute component, wherein the sensing circuitry is controlled to:
receive a scan vector from a first portion of the array of memory cells;
perform a scan chain operation on the scan vector to yield a resulting scan vector; and
write the resulting scan vector to a second portion of the array of memory cells; and
a controller coupled to the sensing circuitry and configured to cause a vector resulting from performance of an exclusive-or (XOR) operation to be combined with a global resultant vector.
17. A system, comprising:
a host;
a memory device coupled to the host and comprising an array of memory cells coupled to sensing circuitry, wherein the memory device is configured to:
receive a scan vector from a first portion of the array;
break the scan vector into multiple portions responsive to a determination that the scan vector exceeds a threshold length;
perform a scan chain operation on the scan vector to generate a resulting scan vector; and
write the resulting scan vector to a second portion of the array.
18. The system of claim 17 , wherein the memory device is further configured to perform the scan chain operation on the multiple portions of the scan vector in parallel.
19. The system of claim 17 , wherein the memory device is further configured to perform the scan chain operation on the multiple portions of the scan vector in series.
20. A method, comprising:
receiving a scan chain vector from a first portion of a memory array;
storing the scan vector in sensing circuitry having a sense amplifier and a compute component;
performing a scan chain operation on the scan vector using the sensing circuitry;
transferring the resulting scan vector to a second portion of the memory array; and
generating an indication that a scan test is successful in response to a determination that the resultant scan vector and an expected output scan vector have greater than a threshold number of data values in common.