Preventing Information Leakage In Out-Of-Order Machines Due To Misspeculation
Typical out-of-order machines can be exploited by security vulnerabilities, such as Meltdown and Spectre, that enable data leakage during misspeculation events. A method of preventing such information leakage includes storing information regarding multiple states of an out-of-order machine to a reorder buffer. This information includes the state of instructions, as well as an indication of data moved to a cache in the transition between states. In response to detecting a misspeculation event at a later state, access to at least a portion of the cache storing the data can be prevented.
1 . A method, comprising:
storing information regarding a first state of an out-of-order machine to a reorder buffer, the information indicating a state of at least one register;
storing information regarding a second state of the out-of-order machine to the reorder buffer, the information indicating whether data is moved to a cache during transition from the first state to the second state; and
in response to detecting a misspeculation event of the second state, preventing access to at least a portion of the cache storing the data.
2 . The method of claim 1 , wherein the preventing access includes invalidating the at least a portion of the cache storing the data.
3 . The method of claim 1 , wherein the preventing access includes invalidating an entirety of the cache.
4 . The method of claim 1 , wherein the cache includes a d-cache.
5 . The method of claim 1 , wherein the cache includes at least one of a branch target cache, a branch target buffer, a store-load dependence predictor, an instruction cache, a translation buffer, a second level cache, a last level cache, and a DRAM cache.
6 . The method of claim 1 , further comprising, in response to detecting the misspeculation event, invalidating at least one of a branch predictor, a branch target cache, a branch target buffer, a store-load dependence predictor, an instruction cache, a translation buffer, a second level cache, a last level cache, and a DRAM cache.
7 . The method of claim 1 , wherein the information regarding the second state includes an indication of a location of cache blocks storing the data.
8 . The method of claim 1 , wherein the information regarding the second state includes an indication of cache blocks created during execution of one or more operations associated with the misspeculation event.
9 . The method of claim 1 , further comprising identifying, based on the information regarding the second state, cache blocks created during execution of operations associated with the misspeculation event.
10 . The method of claim 1 , wherein the misspeculation event occurs during a load/store operation executed by the machine.
11 . The method of claim 10 , wherein the first state corresponds to a state of the machine prior to execution of the load/store operation, and wherein the second state corresponds to a state of the machine after the execution of the load/store operation.
12 . An out-of-order machine comprising:
a cache;
a processor configured to execute an instruction;
a reorder buffer; and
a controller configured to:
store information regarding a first state of the out-of-order machine to the reorder buffer prior to execution of the instruction;
store information regarding a second state of the out-of-order machine to the reorder buffer following execution of the instruction, the information indicating whether data is moved to the cache between the first and second states; and
in response to detecting a misspeculation event of the second state, prevent access to at least a portion of the cache storing the data.
13 . The machine of claim 12 , wherein the controller is further configured to prevent access by invalidating the at least a portion of the cache storing the data.
14 . The machine of claim 12 , wherein the controller is further configured to prevent access by invalidating an entirety of the cache.
15 . The machine of claim 12 , wherein the cache includes a d-cache.
16 . The machine of claim 12 , wherein the cache includes at least one of a branch target cache, a branch target buffer, a store-load dependence predictor, an instruction cache, a translation buffer, a second level cache, a last level cache, and a DRAM cache.
17 . The machine of claim 12 , wherein the controller is further configured, in response to detecting the misspeculation event, to invalidate at least one of a branch predictor, a branch target cache, a branch target buffer, a store-load dependence predictor, an instruction cache, a translation buffer, a second level cache, a last level cache, and a DRAM cache.
18 . The machine of claim 12 , wherein the information regarding the second state includes an indication of a location of cache blocks storing the data.
19 . The machine of claim 12 , wherein the information regarding the second state includes an indication of cache blocks created during execution of one or more operations associated with the misspeculation event.
20 . The machine of claim 12 , wherein the controller is further configured to identify, based on the information regarding the second state, cache blocks created during execution of operations associated with the misspeculation event.
21 . The machine of claim 12 , wherein the misspeculation event occurs during a load/store operation executed by the machine.
22 . The machine of claim 20 , wherein the first state corresponds to a state of the machine prior to execution of the load/store operation, and wherein the second state corresponds to a state of the machine after the execution of the load/store operation.