IP Library Granted Patent US 10,783,134
Granted Patent B2
US 10,783,134 · App. 16/050,818 · Granted Sep 22, 2020

Polling process for monitoring interdependent hardware components

Inventor: Yuri Chernyavsky (Petach Tiqwa, IL)
Assignee: EMC IP Holding Company LLC
G06F16/2343G06F16/2379
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Quick Facts
Patent No.
US 10,783,134
App. No.
16/050,818
Granted
Sep 22, 2020
Kind
B2
Abstract

Systems and methods are provided to implement a polling process for monitoring a system of interdependent hardware components. A shared aggregate state data structure comprising information of an aggregate state of the interdependent hardware components is maintained in a system memory. A poller loop process generates and utilizes two local instances in system memory of the shared aggregate state data structure, including a current state data structure and a previous state data structure. The current state data structure is utilized during a lock-free polling routine to store current aggregate state data of the interdependent hardware components, while other executing threads outside the poller loop process can access the shared aggregate state data structure. The shared aggregate state data structure is updated by performing a merge of state information contained in the shared aggregate state, current aggregate state, and previous aggregate state data structures.

Claims (72)

1. A method, comprising:

maintaining a first data structure in a system memory, wherein the first data structure comprises aggregate state information of a set of interdependent hardware components of a computing system;

performing a poller loop process to update the aggregate state information contained in the first data structure, wherein performing the poller loop process comprises:

acquiring a lock on the first data structure in the system memory;

copying the aggregate state information of the first data structure into a second data structure and a third data structure in the system memory, wherein the aggregate state information of the second data structure is maintained as previous aggregate state information, and wherein the third data structure is maintained and updated with current aggregate state information;

releasing the lock on the first data structure in the system memory after copying the aggregate state information of the first data structure into the second and third data structures in the system memory;

performing a lock-free poller routine to collect current aggregate state information of the set of interdependent hardware components of the computing system, and store the currently collected aggregate state information into the third data structure in the system memory;

reacquiring the lock on the first data structure in the system memory;

updating the aggregate state information of the first data structure based on state information contained in at least one of the second data structure and the third data structure; and

releasing the reacquired lock on the first data structure after updating the aggregate state information of the first data structure.

2. The method of claim 1 , further comprising:

determining whether the currently collected aggregate state information comprises inconsistent device state information; and

discarding the currently collected aggregate state information in response to determining that the currently collected aggregate state information comprises inconsistent device state information.

3. The method of claim 1 , further comprising:

before updating the aggregate state information of the first data structure, determining whether the currently collected aggregate state information in the third data structure in the system memory is inconsistent with the aggregate state information of the first data structure in the system memory; and

discarding the currently collected aggregate state information in response to determining that the currently collected aggregate state information in the third data structure in the system memory is inconsistent with the aggregate state information of the first data structure in the system memory.

4. The method of claim 1 , further comprising:

before updating the aggregate state information of the first data structure, determining whether the aggregate state information of the first data structure comprises device state information which has been modified; and

discarding the currently collected aggregate state information in response to determining that the aggregate state information of the first data structure comprises device state information which has been modified.

5. The method of claim 4 , wherein determining whether the aggregate state information of the first data structure comprises device state information which has been modified comprises determining if a flag for the first data structure has been asserted by an application thread, wherein the asserted flag indicates that the device state information in the first data structure has been modified by the application thread.

6. The method of claim 1 , wherein updating the aggregate state information of the first data structure based on state information contained in at least one of the second data structure and the third data structure comprises:

determining whether a data value in a given field of the first data structure has changed relative to a data value in a corresponding field of the previous state maintained in the second data structure; and

maintaining the data value in the given field of the first data structure in response to determining that the data value in the given field of the first data structure has changed relative to the data value in the corresponding field of the previous state maintained in the second data structure.

7. The method of claim 6 , further comprising updating the data value in the given field of the first data structure using a current data value in a corresponding field of the current state maintained in the third data structure in system memory, in response to determining that the data value in the given field of the first data structure has not changed relative to the data value in the corresponding field of the previous state maintained in the second data structure.

8. The method of claim 1 , wherein the second data structure maintains a read-only copy of the aggregate state information.

9. The method of claim 1 , wherein the set of interdependent hardware components comprises storage devices of a data storage system.

10. An article of manufacture comprising a processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code is executable by one or more processors to implement a process comprising:

maintaining a first data structure in a system memory, wherein the first data structure comprises aggregate state information of a set of interdependent hardware components of a computing system;

performing a poller loop process to update the aggregate state information contained in the first data structure, wherein performing the poller loop process comprises:

acquiring a lock on the first data structure in the system memory;

copying the aggregate state information of the first data structure into a second data structure and a third data structure in the system memory, wherein the aggregate state information of the second data structure is maintained as previous aggregate state information, and wherein the third data structure is maintained and updated with current aggregate state information;

releasing the lock on the first data structure in the system memory after copying the aggregate state information of the first data structure into the second and third data structures in the system memory;

performing a lock-free poller routine to collect current aggregate state information of the set of interdependent hardware components of the computing system, and store the currently collected aggregate state information into the third data structure in the system memory;

reacquiring the lock on the first data structure in the system memory;

updating the aggregate state information of the first data structure based on state information contained in at least one of the second data structure and the third data structure; and

releasing the reacquired lock on the first data structure after updating the aggregate state information of the first data structure.

11. The article of manufacture of claim 10 , further comprising program code which is executable by the one or more processors to implement a process comprising:

determining whether the currently collected aggregate state information comprises inconsistent device state information; and

discarding the currently collected aggregate state information in response to determining that the currently collected aggregate state information comprises inconsistent device state information.

12. The article of manufacture of claim 10 , further comprising program code which is executable by the one or more processors to implement a process comprising:

before updating the aggregate state information of the first data structure, determining whether the currently collected aggregate state information in the third data structure in the system memory is inconsistent with the aggregate state information of the first data structure in the system memory; and

discarding the currently collected aggregate state information in response to determining that the currently collected aggregate state information in the third data structure in the system memory is inconsistent with the aggregate state information of the first data structure in the system memory.

13. The article of manufacture of claim 10 , further comprising program code which is executable by the one or more processors to implement a process comprising:

before updating the aggregate state information of the first data structure, determining whether the aggregate state information of the first data structure comprises device state information which has been modified; and

discarding the currently collected aggregate state information in response to determining that the aggregate state information of the first data structure comprises device state information which has been modified.

14. The article of manufacture of claim 13 , wherein determining whether the aggregate state information of the first data structure comprises device state information which has been modified comprises determining if a flag for the first data structure has been asserted by an application thread, wherein the asserted flag indicates that the device state information in the first data structure has been modified by the application thread.

15. The article of manufacture of claim 10 , wherein updating the aggregate state information of the first data structure based on state information contained in at least one of the second data structure and the third data structure comprises:

determining whether a data value in a given field of the first data structure has changed relative to a data value in a corresponding field of the previous state maintained in the second data structure;

maintaining the data value in the given field of the first data structure in response to determining that the data value in the given field of the first data structure has changed relative to the data value in the corresponding field of the previous state maintained in the second data structure; and

updating the data value in the given field of the first data structure using a current data value in a corresponding field of the current state maintained in the third data structure in system memory, in response to determining that the data value in the given field of the first data structure has not changed relative to the data value in the corresponding field of the previous state maintained in the second data structure.

16. The article of manufacture of claim 10 , wherein the second data structure maintains a read-only copy of the aggregate state information.

17. A system comprising:

a computing system comprising a hardware infrastructure comprising a set of interdependent hardware components; and

a computing node comprising at least one processor, and system memory comprising program instructions stored in the system memory, wherein the program instructions are executable by the at least one processor to perform a process comprising:

maintaining a first data structure in the system memory, wherein the first data structure comprises aggregate state information of the set of interdependent hardware components of the computing system;

performing a poller loop process to update the aggregate state information contained in the first data structure, wherein performing the poller loop process comprises:

acquiring a lock on the first data structure in the system memory;

copying the aggregate state information of the first data structure into a second data structure and a third data structure in the system memory, wherein the aggregate state information of the second data structure is maintained as previous aggregate state information, and wherein the third data structure is maintained and updated with current aggregate state information;

releasing the lock on the first data structure in the system memory after copying the aggregate state information of the first data structure into the second and third data structures in the system memory;

performing a lock-free poller routine to collect current aggregate state information of the set of interdependent hardware components of the computing system, and store the currently collected aggregate state information into the third data structure in the system memory;

reacquiring the lock on the first data structure in the system memory;

updating the aggregate state information of the first data structure based on state information contained in at least one of the second data structure and the third data structure; and

releasing the reacquired lock on the first data structure after updating the aggregate state information of the first data structure.

18. The system of claim 17 , wherein the program instructions are executable by the at least one processor to perform a process comprising:

determining whether the currently collected aggregate state information comprises inconsistent device state information, and discarding the currently collected aggregate state information in response to determining that the currently collected aggregate state information comprises inconsistent device state information;

before updating the aggregate state information of the first data structure, determining whether the currently collected aggregate state information in the third data structure in the system memory is inconsistent with the aggregate state information of the first data structure in the system memory, and discarding the currently collected aggregate state information in response to determining that the currently collected aggregate state information in the third data structure in the system memory is inconsistent with the aggregate state information of the first data structure in the system memory; and

before updating the aggregate state information of the first data structure, determining whether the aggregate state information of the first data structure comprises device state information which has been modified, and discarding the currently collected aggregate state information in response to determining that the aggregate state information of the first data structure comprises device state information which has been modified.

19. The system of claim 17 , wherein updating the aggregate state information of the first data structure based on state information contained in at least one of the second data structure and the third data structure comprises:

determining whether a data value in a given field of the first data structure has changed relative to a data value in a corresponding field of the previous state maintained in the second data structure;

maintaining the data value in the given field of the first data structure in response to determining that the data value in the given field of the first data structure has changed relative to the data value in the corresponding field of the previous state maintained in the second data structure; and

updating the data value in the given field of the first data structure using a current data value in a corresponding field of the current state maintained in the third data structure in system memory, in response to determining that the data value in the given field of the first data structure has not changed relative to the data value in the corresponding field of the previous state maintained in the second data structure.

20. The system of claim 17 , wherein the computing system comprises a data storage system and wherein the set of interdependent hardware components comprises storage devices of the data storage system.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (047648/0422) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060160/0862 →
RELEASE OF SECURITY INTEREST AT REEL 047648 FRAME 0346 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058298/0510 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Oct 12, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 047648/0346 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Oct 12, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 047648/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2018
From: CHERNYAVSKY, YURI
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 046515/0795 →