Write level arbiter circuitry
Devices and methods include utilizing memory including a group of storage elements, such as memory banks. A command interface is configured to receive a write command to write data to the memory. A data strobe is received to assist in writing the data to the memory. Phase division circuitry is configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory. Arbiter circuitry is configured to detect which phase of the plurality of phases captures a write start signal for the write command.
1. A semiconductor device comprising:
memory comprising a group of storage elements;
a command interface configured to receive a write command to write data to the memory;
a data strobe pin configured to receive a data strobe to assist in writing the data to the memory;
phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory; and
arbiter circuitry configured to detect which phase of the plurality of phases captures a write start signal for the write command, wherein the arbiter circuitry comprises a latch that is configured to:
receive a first indication of a pulse in a first phase of the plurality of phases; and
receive a second indication of a pulse in a second phase of the plurality of phases.
2. The semiconductor device of claim 1 , wherein the plurality of phases comprises four phases.
3. The semiconductor device of claim 2 , wherein:
a first phase of the plurality of phases corresponds to rising edges of a first set of pulses of the data strobe;
a second phase of the plurality of phases corresponds to falling edges of the first set of pulses of the data strobe;
a third phase of the plurality of phases corresponds to rising edges of a second set of pulses of the data strobe, wherein each pulse of the second set of pulses occurs between two pulses of the first set of pulses; and
a fourth phase of the plurality of phases corresponds to falling edges of the second set of pulses of the data strobe.
4. The semiconductor device of claim 1 , wherein the latch is configured to:
output a third indication when the pulse in the first phase occurs before the pulse in the second phase after a reset of the arbiter circuitry; or
output a fourth indication when the pulse in the second phase occurs before the pulse in the first phase after the reset of the arbiter circuitry.
5. The semiconductor device of claim 4 , wherein the latch is configured to:
suppress the fourth indication when the latch outputs the third indication; and
suppress the third indication when the latch outputs the fourth indication.
6. The semiconductor device of claim 1 , comprising a first flip-flop that is configured to receive the pulse in the first phase and to output the first indication when the pulse in the first phase is received.
7. The semiconductor device of claim 6 , comprising a second flip-flop that is configured to receive the pulse in the second phase and to output the second indication when the pulse in the first phase is received.
8. The semiconductor device of claim 1 , comprising:
a first capture flip-flop configured to capture the write start signal using the first phase; and
a second capture flip-flop configured to capture the write start signal using the second phase.
9. The semiconductor device of claim 8 , comprising:
a first suppression flip-flop configured to suppress or pass an output of the first capture flip-flop based at least in part on the first indication; and
a second suppression flip-flop configured to suppress or pass an output of the second capture flip-flop based at least in part on the second indication.
10. The semiconductor of claim 9 , wherein the suppression or passing of the outputs of the first and second capture flip-flops is based at least in part on a length of a preamble of the write command.
11. A semiconductor device comprising:
a plurality of memory cells;
a command interface configured to receive a write command to write data to the memory cells;
a data strobe pin configured to receive a data strobe to assist in writing the data to the memory cells;
phase division circuitry configured to receive and divide a data strobe into a plurality of phases to be used in writing the data to the memory cells, wherein the data strobe is configured to assist in writing the data to the memory cells;
arbiter circuitry configured to detect which phase of the plurality of phases captures a write start signal for the write command, wherein the detection of the plurality of phases is based at least in part on a preamble length for the write command;
a first capture flip-flop configured to capture the write start signal at a first data input using a first phase of the plurality of phases as a clock for the first capture flip-flop; and
a second capture flip-flop configured to capture the write start signal at a second data input using a second phase of the plurality of phases as a clock for the second capture flip-flop.
12. The semiconductor device of claim 11 , comprising:
a first suppression flip-flop configured to suppress or pass an output of the first capture flip-flop based at least in part on the first phase and the preamble length for the write command; and
a second suppression flip-flop configured to suppress or pass an output of the second capture flip-flop based at least in part on the second phase and the preamble length for the write command.
13. The semiconductor device of claim 12 , wherein the output of the first capture flip-flop is passed to an input of the first suppression flip-flop, a clock input of the first suppression flip-flop is based at least in part on the first phase, the output of the second capture flip-flop is passed to an input of the second suppression flip-flop, and a clock input of the second suppression flip-flop is based at least in part on the second phase.
14. The semiconductor device of claim 13 , wherein the first capture flip-flop, the second capture flip-flop, the first suppression flip-flop, and the second suppression flip-flop are configured to receive a reset signal to reset the first capture flip-flop, the second capture flip-flop, the first suppression flip-flop, and the second suppression flip-flop to their respective initial states.
15. A method comprising:
receiving a write command at a command interface of a memory device;
receiving a data strobe to assist in writing data to memory of the memory device;
dividing, using phase divider circuitry, the data strobe into a plurality of phases to be used in writing the data to the memory; and
detecting, using arbiter circuitry, which phase of the plurality of phases captures a write start signal for the write command, wherein detecting the phase of the plurality of phases comprises outputting a write leveling output signal as an indication of the detected phase, and detecting the phase is based at least in part on a length of preamble for the write command.
16. The method of claim 15 , wherein detecting which phase of the plurality of phases captures a write start signal comprises detecting whether the write start signal is captured by a subset of the plurality of phases.
17. The method of claim 16 , wherein the subset of the plurality of phases comprises phases of the plurality of phases that correspond to falling edges of the data strobe.