Fast non-volatile storage device recovery techniques
Techniques are disclosed herein for providing accelerated recovery techniques of a memory device. Such techniques can allow for recovery of the memory device, such as, but not limited to, a flash memory device, following an unexpected reset event.
1. A method comprising:
at a first start-up of a memory device, comparing a general status element of a reset accelerator register of the memory device to a first uncompleted threshold;
determining on the first start-up of the memory device that the general status element indicates an uncompleted memory operation, and in response to such determining, comparing specific status elements of the reset accelerator register to a second uncompleted threshold to determine one or more specific uncompleted memory operations, the specific status elements each indicative of a status of a respective specific memory operation of a group of specific memory operations;
executing clean-up recovery operations associated with each specific memory operation of the group of memory operations indicated as uncompleted via the specific status elements of the reset accelerator register; and
determining on a second start-up of the memory device that the general status element does not indicate an uncompleted memory operation, and in response to such determining enabling the memory device to respond to host commands.
2. The method of claim 1 , including, at memory device start-up, not resetting the reset accelerator register.
3. The method of claim 1 , wherein
if a first specific status element of the specific status elements does not satisfy the uncompleted threshold in response to a comparison, checking a second specific status element of the reset accelerator register; and
if the first specific status element satisfies the uncompleted threshold in response to the comparison, executing a first clean-up recovery operation to complete an operation of the memory device that was in-process before the last shutdown of the memory device prior to the start-up.
4. The method of claim 3 , wherein the first specific status element s indicative of a garbage collection operation.
5. The method of claim 3 , wherein the first specific status element is indicative of a refresh operation.
6. The method of claim 3 , wherein the first specific status element is indicative of a wear leveling operation.
7. The method of claim 3 , wherein the first specific status element s indicative of a block retirement operation.
8. The method of claim 3 , wherein the first specific status element is indicative of a host read or write operation.
9. The method of claim 3 , wherein the first specific status element is indicative of a power-on recovery operation.
10. A memory device comprising:
a group of non-volatile memory cells;
a non-volatile, reset accelerator register;
a processing device operably coupled to the group of non-volatile memory cells, the processing device configured to perform operations comprising:
initiate a first memory operation of a number of memory operations on the group of non-volatile memory cells;
set a general indication of a reset accelerator register to indicate any one of the number of memory operations is initiated and not completed;
set a first indication of the reset accelerator register to indicate the first memory operation is initiated and not completed; and
reset the first indication in response to completion of the first memory operation; and
wherein, upon start-up of the memory device, the processing device is further configured to perform operations comprising:
compare the general indication of the reset accelerator register to a first threshold;
compare the first indication of the reset accelerator register to an uncompleted threshold when the general indication satisfies the first threshold; and
finish the first memory operation when the first indication satisfies the uncompleted threshold.
11. The memory device of claim 10 , wherein the operation to finish the first memory operation includes retrieving a physical address of the memory device from a record of the reset accelerator register mapped to the first indication, the physical address associated with an area of non-volatile memory cells of the group of non-volatile memory cells associated with the first memory operation.
12. The memory device of claim 10 , wherein the first indication is indicative of garbage collection of a block of data.
13. The memory device of claim 10 , wherein the first indication is indicative of a refresh of a data block.
14. The memory device of claim 10 , wherein the first indication is indicative of a wear leveling operation.
15. The memory device of claim 10 , wherein the first indication is indicative of read error handling.
16. The memory device of claim 10 , wherein the first indication is indicative of write error handling.
17. The memory device of claim 10 , wherein the first indication is indicative of block retirement.
18. The memory device of claim 10 , wherein the first indication is indicative of handling a host write operation.
19. The memory device of claim 10 , wherein the first indication is indicative of handling a host read activity.