Status management in storage backed memory package
Devices and techniques for status management in storage backed memory are disclosed herein. An encoded message can be received at a first interface of the memory package. Here, the memory package also includes a second interface to a host. The message can be decoded to obtain a decoded message that includes an attribute. The attribute can be compared a set of attributes that correspond to an advertised status of the memory package. The comparison enables a determination that the attribute is in the set of attributes. The advertised status of the memory package can then be modified in response to the determination that the attribute is in the set of attributes.
1. A hardware memory package comprising:
a memory controller;
a volatile portion;
a non-volatile portion;
a first interface that enables communication between the memory controller and the host, the first interface receiving an encoded message from the host;
a second interface that enables communication between the volatile portion and the host; and
a decoder coupled to the first interface, the decoder to perform operations comprising:
decoding the encoded message to obtain a decoded message that comprises a request to write to a command register of the memory controller and further comprises a message attribute;
prior to providing the decoded message to a component of the memory controller for executing the request to write to the command register:
inspecting the decoded message to determine whether the request to write to the command register is associated with an operation that corresponds to an advertised status of the hardware memory package, the inspecting the decoded message comprising determining whether the message attribute is in a set of attributes that corresponds to the advertised status by comparing the message attribute to the set of attributes, the advertised status being accessible by the host via the first interface; and
modifying the advertised status of the hardware memory package in response to determining that the message attribute is in the set of attributes; and
providing the decoded message to the component of the memory controller.
2. The hardware memory package of claim 1 , wherein the second interface is a double data rate (DDR) random-access memory (RAM) interface.
3. The hardware memory package of claim 2 , wherein the hardware memory package is a non-volatile dual in-line memory module (NVDIMM).
4. The hardware memory package of claim 1 , wherein the advertised status indicates whether the operation in progress for the memory controller.
5. The hardware memory package of claim 1 , wherein the set of attributes are defined by a Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backed Interface (BAEBI) family of standards.
6. The hardware memory package of claim 1 , wherein the attribute is an address.
7. The hardware memory package of claim 6 , wherein the address is a page designator.
8. A method comprising:
receiving, at a first interface of a hardware memory package, an encoded message from a host, the first interface enabling communication between a memory controller and the host, the hardware memory package comprising the memory controller and a second interface that enables communication between a volatile portion of the hardware memory package and the host;
decoding the encoded message to obtain a decoded message that comprises a request to write to a command register of the memory controller and further comprises a message attribute;
prior to providing the decoded message to a component of the memory controller for executing the request to write to the command register:
inspecting the decoded message to determine whether the request to write to the command register is associated with an operation that corresponds to an advertised status of the hardware memory package, the inspecting the decoded message comprising determining whether the message attribute is in a set of attributes that corresponds to the advertised status by comparing the message attribute to the set of attributes, the advertised status being accessible by the host via the first interface; and
modifying the advertised status of the hardware memory package in response to determining that the message attribute is in the set of attributes; and
providing the decoded message to the component of the memory controller.
9. The method of claim 8 , wherein the second interface is a double data rate (DDR) random-access memory (RAM) interface.
10. The method of claim 9 , wherein the hardware memory package is a non-volatile dual in-line memory module (NVDIMM).
11. The method of claim 8 , wherein the advertised status indicates whether the operation in progress for the memory controller.
12. The method of claim 8 , wherein the set of attributes are defined by a Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backed Interface (BAEBI) family of standards.
13. The method of claim 8 , wherein the attribute is an address.
14. The method of claim 13 , wherein the address is a page designator.
15. At least one non-transitory machine readable medium including instructions, when executed by processing circuitry of a hardware memory package, cause the hardware memory package to perform operations comprising:
receiving, at a first interface of the hardware memory package, an encoded message from a host, the first interface enabling communication between a memory controller and the host, the hardware memory package comprising the memory controller and a second interface that enables communication between a volatile portion of the hardware memory package and the host;
decoding the encoded message to obtain a decoded message that comprises a request to write to a command register of the memory controller and further comprises a message attribute;
prior to providing the decoded message to a component of the memory controller for executing the request to write to the command register:
inspecting the decoded message to determine whether the request to write to the command register is associated with an operation that corresponds to an advertised status of the hardware memory package, the inspecting the decoded message comprising determining whether the message attribute is in a set of attributes that corresponds to the advertised status by comparing the message attribute to the set of attributes, the advertised status being accessible by the host via the first interface; and
modifying the advertised status of the hardware memory package in response to determining that the message attribute is in the set of attributes; and
providing the decoded message to the component of the memory controller.
16. The at least one non-transitory machine readable medium of claim 15 , wherein the second interface is a double data rate (DDR) random-access memory (RAM) interface.
17. The at least one non-transitory machine readable medium of claim 16 , wherein the hardware memory package is a non-volatile dual in-line memory module (NVDIMM).
18. The at least one non-transitory machine readable medium of claim 15 , wherein the advertised status indicates whether the operation in progress for the memory controller.
19. The at least one non-transitory machine readable medium of claim 15 , wherein the attribute is an address.
20. The at least one non-transitory machine readable medium of claim 19 , wherein the address is a page designator.