Apparatus and method for unified system power button behavior across different information handling system architectures
An information handling system includes a chipset component configured to implement one of two hardware architectures, and a power button circuit coupled to the chipset component. The power button circuit receives an input signal from an assertion of a power button. The power button circuit further determines that the chipset implements the first hardware architecture and provides a first output signal to the chipset component in response. The first output signal is based on the input signal. The power button circuit further determines that the chipset component implements the second hardware architecture, and provides a second output signal to the chipset component in response. The second output signal is based on the input signal for a first predetermined time, followed by a pulse to the chipset component for a second predetermined time.
1. An information handling system based on one of a first hardware architecture and a second hardware architecture, the information handling system comprising:
a chipset component configured to implement one of the first or second hardware architectures; and
a power button circuit coupled to the chipset component, the power button circuit configured to:
receive an input signal from an assertion of a power button;
determine that the chipset component is configured to implement the first hardware architecture;
provide a first output signal to the chipset component in response to determining that the chipset component is configured to implement the first hardware architecture, the first output signal being based on the input signal;
determine that the chipset component is configured to implement the second hardware architecture; and
provide a second output signal to the chipset component in response to determining that the chipset component is configured to implement the second hardware architecture, the second output signal being based on the input signal for a first predetermined time, followed by a pulse to the chipset component for a second predetermined time, wherein when the chipset component implements the first hardware architecture, the chipset component responds to a falling edge of the first output signal to power down the information handling system.
2. The information handling system of claim 1 , wherein when the chipset component implements the second hardware architecture, the chipset component responds to a rising edge of the second output signal to power down the information handling system.
3. The information handling system of claim 1 , wherein the input signal from the power button comprises a transition from a logic low (0) state to a logic high (1) state.
4. The information handling system of claim 3 , wherein the first output signal comprises a transition from the logic high (1) state to the logic low (0) state.
5. The information handling system of claim 3 , wherein the second output signal comprises a transition from the logic high (1) state to the logic low (0) state for the first predetermined time and wherein the pulse comprises the logic high (1) state for the second predetermined time.
6. The information handling system of claim 1 , wherein:
when the chipset component implements the first hardware architecture, the power button circuit is further configured to determine that the input signal remains asserted for longer than a push button override time; and
the chipset component is configured to shut down the information handling system in response to the determination that the input signal remains asserted for longer than the push button override time.
7. The information handling system of claim 1 , wherein:
when the chipset component implements the second hardware architecture, the power button circuit is further configured to determine that the input signal remains asserted for longer than a sum of the first predetermined time, the second predetermined time, and a push button override time; and
the chipset component is configured to shut down the information handling system in response to the determination that the input signal remains asserted for longer than the sum of the first predetermined time, second predetermined time, and the push button override time.
8. The information handling system of claim 1 , wherein when the chipset component is configured to implement the first hardware architecture, the chipset component is based upon an Intel architecture.
9. The information handling system of claim 1 , wherein when the chipset component is configured to implement the second hardware architecture, the chipset component is based upon an AMD architecture.
10. A method for providing a power button input for an information handling system, wherein the information handling system is based on one of a first hardware architecture and a second hardware architecture, the method comprising:
receiving, by a power button circuit of the information handling system coupled to a chipset component of the information handling system, an input signal from an assertion of a power button of the information handling system, wherein the chipset component is configured to implement one of the first or second hardware architectures;
determining, by the power button circuit, that the chipset component is configured to implement the first hardware architecture;
providing, by the power button circuit, a first output signal to the chipset component in response to determining that the chipset component is configured to implement the first hardware architecture, the first output signal being based on the input signal;
determining, by the power button circuit, that the chipset component is configured to implement the second hardware architecture;
providing a second output signal to the chipset component in response to determining that the chipset component is configured to implement the second hardware architecture, the second output signal being based on the input signal for a first predetermined time, followed by a pulse to the chipset component for a second predetermined time; and
when the chipset component implements the second hardware architecture, responding, by the chipset component, to a rising edge of the second output signal to power down the information handling system.
11. The method of claim 10 , wherein when the chipset component implements the first hardware architecture, the method further comprises:
responding, by the chipset component, to a falling edge of the first output signal to power down the information handling system.
12. The method of claim 10 , wherein the input signal from the power button comprises a transition from a logic low (0) state to a logic high (1) state.
13. The method of claim 12 , wherein the first output signal comprises a transition from the logic high (1) state to the logic low (0) state.
14. The method of claim 12 , wherein the second output signal comprises a transition from the logic high (1) state to the logic low (0) state for the first predetermined time and wherein the pulse comprises the logic high (1) state for the second predetermined time.
15. The method of claim 10 , further comprising:
determining, by the power button circuit when the chipset component implements the first hardware architecture, that the input signal remains asserted for longer than a push button override time; and
shutting down, by the chipset component, the information handling system in response to the determination that the input signal remains asserted for longer than the push button override time.
16. The method of claim 10 , further comprising:
determining, by the power button circuit when the chipset component implements the second hardware architecture, that the input signal remains asserted for longer than a sum of the first predetermined time, the second predetermined time, and a+ push button override time; and
shutting down, by the chipset component, the information handling system in response to the determination that the input signal remains asserted for longer than the sum of the first predetermined time, the second predetermined time, and the push button override time.
17. The method of claim 10 , wherein when the chipset component is configured to implement the first hardware architecture, the chipset component is based upon an Intel architecture, and when the chipset component is configured to implement the second hardware architecture, the chipset component is based upon an AMD architecture.
18. A power button circuit for an information handling system, the power button circuit comprising:
a push button including an output terminal, the push button configured to provide a logic low signal when the push button is activated and to provide a logic high signal when the push button is not activated;
a timer circuit including an input terminal coupled to the output terminal of the push button, and an output terminal;
a rising-edge detector circuit including an input terminal coupled to the output terminal of the timer circuit, and an output terminal;
a pulse circuit including an input terminal coupled to the output terminal of the rising-edge detector circuit, and an output terminal, the pulse circuit configured to output a pulse signal of a predetermined duration in response to the output of the rising-edge detector circuit;
an AND-gate including a first input terminal coupled to the output terminal of the pulse circuit, a second input terminal, and an output terminal;
an architecture selection element configured to store a first state when the information handling system is based on a first hardware architecture, and to store a second state when the information handling system is based on a second hardware architecture, the architecture selection element including an output terminal coupled to the second input terminal of the AND-gate; and
an OR-gate including a first input terminal coupled to the output terminal of the AND-gate, a second input terminal coupled to the output terminal of the push button, and an output to provide a push button signal to a chipset component of the information handling system, the chipset component being configured to implement one of the first or second hardware architectures for the information handling system.