Data protection in computer processors
View Patent ↗Systems, apparatuses, and methods related to a computer system having a processor and a main memory storing scrambled data are described. The processor may have a cache, a register, an execution unit, and an unscrambler. The processor can load the scrambled data into the cache; and the unscrambler may convert the scrambled data into unscrambled data just in time for the register or the execution unit during instruction execution. The unscrambled data can be an instruction, an address, or an operand of an instruction. Unscrambling can be performed just before loading the data item in a scrambled form from the cache into the register in an unscrambled form, or after the data item leaves the register in the scrambled form as input to the execution unit in the unscrambled form. The unscrambled data and the scrambled data may have the same set of bits arranged in different orders.
1. A computer system, comprising:
a memory configured to store scrambled data;
a processor coupled with the memory, wherein the processor is packaged in an integrated circuit chip; and the memory is separate from the integrated circuit chip, the processor having:
a cache;
a register;
an execution unit;
an unscrambler, wherein the processor is configured to load the scrambled data into the cache, wherein the unscrambler is configured to convert the scrambled data in the cache into unscrambled data for the register or the execution unit; and
a scrambler, wherein the scrambler is configured to convert a result of the execution unit into a scrambled form for storing in the cache, the memory, or a storage device;
an external cache coupled between the memory and the processor to cache the scrambled data for the processor; and
a second processor having access to the memory or the cache, wherein the second processor is prevented from accessing a key used by the unscrambler to convert the scrambled data into the unscrambled data.
2. The computer system of claim 1 , wherein the scrambled data and the unscrambled data have a same number of bits; and the register has a width that is equal to the number of bits.
3. The computer system of claim 2 , wherein the unscrambled data is an instruction, an address, or an operand of an instruction.
4. The computer system of claim 3 , wherein the unscrambler is configured to convert the scrambled data in the register into the unscrambled data as input to the execution unit, in response to an instruction execution using content of the register.
5. The computer system of claim 3 , wherein the unscrambler is configured to convert the scrambled data into the unscrambled data as input to the register in response to a request to load content into the register.
6. The computer system of claim 2 , wherein the unscrambler includes a plurality of multiplexers; each of the multiplexers is configured to select one bit from the scrambled data according to a key as a corresponding bit of the unscrambled data.
7. The computer system of claim 1 , wherein the scrambled data and the unscrambled data have a same set of bits having different orders from one another.
8. The computer system of claim 1 , wherein the processor is configured to scramble a result generated by the execution unit before the result is stored in a register of the processor or in the cache.
9. A method, comprising:
fetching, from a memory coupled with a processor, a scrambled data item, bits of the scrambled data items are reordered according to scrambling keys;
loading, in an unscrambler of the processor, an unscrambling key for each respective bit of an unscrambled data item to be recovered from the scrambled data item;
selecting, by the unscrambler, the respective bit from the scrambled data item according to the key, in response to instruction execution in the processor involving the unscrambled data item; and
performing the instruction execution using the unscrambled data item;
wherein the unscrambled data item comprises at least an instruction, an address, or an operand of an instruction, or any combination thereof;
wherein the unscrambled data item is generated on a path between loading the unscrambled data item from a cache of the processor and storing the unscrambled data item into a register of the processor.
10. The method of claim 9 , wherein the unscrambled data item is generated on a path between retrieving the unscrambled data item from a register of the processor and inputting the unscrambled data item into an execution unit of the processor.
11. The method of claim 9 , further comprising:
scrambling a result of the instruction execution.
12. A computer processor, comprising:
a register;
an execution unit; and
an unscrambler;
wherein the unscrambler is configured to convert scrambled data into unscrambled data in response to an instruction execution involving the unscrambled data in the register or the execution unit;
wherein the scrambled data and the unscrambled data have a same set of bits arranged in different orders;
wherein for each bit in the unscrambled data, the unscrambler has a multiplexer configured to select, according to a respective unscrambling key, a bit from bits in the scrambled data.
13. The computer processor of claim 12 , wherein an output of the unscrambler is connected to an input of the register to provide the register with the unscrambled data.
14. The computer processor of claim 12 , wherein an input of the unscrambler is coupled to the register to receive the scrambled data from the register; and an output of the unscrambler is coupled to an input of the execution unit to provide the unscrambled data to the execution unit.