IP Library Granted Patent US 10,553,278
Granted Patent B1
US 10,553,278 · App. 16/056,354 · Granted Feb 4, 2020

Media manager cache eviction timer for reads and writes during resistivity drift

Inventors: Ashay Narsale (Newark, CA); Robert M. Walker (Raleigh, NC)
Assignee: MICRON TECHNOLOGY, INC.
G11C13/0061G11C13/003G11C13/004G11C13/0004G11C13/0069G11C13/0097G11C15/046G11C2013/0045G11C2013/0054G11C2013/0078
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Quick Facts
Patent No.
US 10,553,278
App. No.
16/056,354
Granted
Feb 4, 2020
Kind
B1
Abstract

A method for caching memory requests while accounting for a phase change memory cell drift phenomenon is described. The method includes writing first user data to an address in phase change memory cells; setting a timer in a set of data structures to a first value in response to writing the first user data to the phase change memory cells, wherein the data structures are stored outside the phase change memory cells; determining whether the timer corresponding to the first user data has expired; and fulfilling a read request for the address from the set of data structures in response to determining that the timer has not expired.

Claims (63)

1. A method for caching memory requests while accounting for a phase change memory cell drift phenomenon, the method comprising:

writing first user data to an address in phase change memory cells;

setting a timer in a set of data structures to a first value in response to writing the first user data to the phase change memory cells, wherein the set of data structures are stored outside the phase change memory cells;

determining whether the timer, corresponding to the first user data, has expired; and

fulfilling a read request for the address from the set of data structures in response to determining that the timer has not expired.

2. The method of claim 1 , further comprising:

fulfilling the read request for the address from the phase change memory cells in response to determining that the timer has expired.

3. The method of claim 1 , wherein the set of data structures comprise a content addressable memory (CAM) data structure that comprises a first set of entries and a cache data structure that comprises a second set of entries;

wherein each entry in the first set of entries references a separate entry in the second set of entries;

wherein an entry in the second set of entries comprises the first user data; and

wherein an entry in the first set of entries comprises the address, a reference to the entry in the second set of entries, and the timer.

4. The method of claim 1 , further comprising:

receiving a first write request that comprises the first user data and the address;

storing the first user data in the set of data structures in response to receiving the first write request for the first user data; and

setting the timer to a second value in response to storing the first user data in the set of data structures.

5. The method of claim 4 , further comprising:

determining that the timer, set with the second value, has expired, wherein the writing the first user data to the address in the phase change memory cells is performed in response to determining that the timer, set with the second value, has expired.

6. The method of claim 5 , further comprising:

receiving a second write request that comprises second user data and the address;

storing the second user data in the set of data structures in place of the first user data in response to receiving the second write request; and

setting the timer to the second value in response to storing the second user data in the set of data structures.

7. The method of claim 6 , wherein the first value is different from the second value.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

set a timer in a set of data structures to a first value in response to writing first user data to an address in phase change memory cells, wherein the set of data structures are stored outside the phase change memory cells;

determine whether the timer, corresponding to the first user data, has expired; and

fulfill a read request for the address from the phase change memory cells in response to determining that the timer has expired.

9. The non-transitory computer-readable medium of claim 8 , wherein the processing device is further to:

fulfill the read request for the address from the set of data structures in response to determining that the timer has not expired.

10. The non-transitory computer-readable medium of claim 8 , wherein the set of data structures comprise a content addressable memory (CAM) data structure that comprises a first set of entries and a cache data structure that comprises a second set of entries;

wherein each entry in the first set of entries references a separate entry in the second set of entries;

wherein an entry in the second set of entries comprises the first user data; and

wherein an entry in the first set of entries comprises the address, a reference to the entry in the second set of entries, and the timer.

11. The non-transitory computer-readable medium of claim 8 , wherein the processing device is further to:

receive a first write request that comprises the first user data and the address;

store the first user data in the set of data structures in response to receiving the first write request for the first user data; and

set the timer to a second value in response to storing the first user data in the set of data structures.

12. The non-transitory computer-readable medium of claim 11 , wherein the processing device is further to:

determine that the timer, set with the second value, has expired, wherein the writing the first user data to the address in the phase change memory cells is performed in response to determining that the timer, set with the second value, has expired.

13. The non-transitory computer-readable medium of claim 12 , wherein the processing device is further to:

receive a second write request that comprises second user data and the address;

store the second user data in the set of data structures in place of the first user data in response to receiving the second write request; and

set the timer to the second value in response to storing the second user data in the set of data structures.

14. The non-transitory computer-readable medium of claim 13 , wherein the first value is different from the second value.

15. A system comprising:

a memory component; and

a processing device, coupled to the memory component, configured to:

write first user data to an address in phase change memory cells;

set a timer in an entry in a content addressable memory (CAM) data structure of a set of data structures to a first value in response to writing the first user data to the phase change memory cells;

determine whether the timer corresponding to the first user data has expired; and

fulfill a read request for the address from an entry in a cache data structure of the set of data structures in response to determining that the timer has not expired, wherein the CAM data structure and the cache data structure are stored outside the phase change memory cells.

16. The system of claim 15 , wherein the processing device is further configured to:

fulfill the read request for the address from the phase change memory cells in response to determining that the timer has expired.

17. The system of claim 15 , wherein the processing device is further configured to:

receive a first write request that comprises the first user data and the address;

store the first user data in the entry of the cache data structure in response to receiving the first write request for the first user data; and

set the timer to a second value in response to storing the first user data in the set of data structures.

18. The system of claim 17 , wherein the processing device is further configured to:

determine that the timer, set with the second value, has expired, wherein the writing the first user data to the address in the phase change memory cells is performed in response to determining that the timer, set with the second value, has expired.

19. The system of claim 18 , wherein the processing device is further configured to:

receive a second write request that comprises second user data and the address;

store the second user data in the entry of the cache data structure in place of the first user data in response to receiving the second write request; and

set the timer to the second value in response to storing the second user data in the cache data structure of the set of data structures.

20. The system of claim 19 , wherein the first value is different from the second value.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2018
From: NARSALE, ASHAY; WALKER, ROBERT M.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046570/0367 →
Cited By (2)
US 12,379,844 US 12,411,775