2T1C ferro-electric random access memory cell
View Patent ↗A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN) and controlled by a first wordline (WL 1 ), a second transistor coupled between a reference line and the SN and controlled by a second wordline (WL 2 ), and a ferro-capacitor coupled between the SN and a plateline. The device further includes a sense-amplifier coupled to the bit-line and reference line, and a processing-element configured to issue control signals to WL 1 , WL 2 , the plateline and the sense-amplifier. The cell is configured and operated to generate a bit-level reference in which a first voltage pulse is applied to the plateline during a read cycle for the data pulse and a second voltage pulse serves as a reference pulse and as a clear pulse.
1. A method comprising:
discharging a storage node (SN) of a ferroelectric random access memory (F-RAM) cell by turning on a first transistor having a first source-drain (SD) terminal coupled to the SN and a second SD terminal coupled to a bit-line (BL);
generating a data voltage on the BL by applying a first voltage pulse having a peak voltage of V 1 to a plateline of a ferro-capacitor coupled between the plateline and the SN;
decoupling the BL from the SN by turning off the first transistor;
discharging the SN by turning on a second transistor having a first source-drain (SD) terminal coupled to the SN and a second SD terminal coupled to a reference bit-line (BLB); and
generating a reference voltage on the BLB derived from an unswitched (U-term) of the ferro-capacitor of the F-RAM cell by applying a second voltage pulse having a peak voltage of V 2 to the plateline.
2. The method of claim 1 , further comprising:
decoupling the BLB from the SN by turning off the second transistor; and
coupling the data voltage on the BL and the reference voltage on the BLB to a sense amplifier (SA) to read data stored in the F-RAM cell.
3. The method of claim 1 , wherein applying the second voltage pulse having the peak voltage of V 2 to the plateline further serves as a clear pulse to harden the U-term in the ferro-capacitor.
4. The method of claim 1 , wherein V 2 is greater than V 1 .
5. The method of claim 1 , further comprising coupling the BL to a bit-line pre-charge circuit and pre-charging the BL to a predetermined voltage prior to discharging the SN.
6. The method of claim 5 , wherein discharging the SN comprises discharging the SN through the bit-line pre-charge circuit.
7. The method of claim 6 further comprising decoupling the BL from the bit-line pre-charge circuit prior to applying the first voltage pulse and wherein the bit-line pre-charge circuit remains electrically decoupled from the bit-line during a time between the first voltage pulse and the second voltage pulse.
8. The method of claim 1 , wherein a bit-line capacitance is substantially equal to a reference bit-line capacitance.
9. The method of claim 1 , wherein a bit-line capacitance is greater than a reference bit-line capacitance.
10. A method comprising:
discharging a storage node (SN) of a ferroelectric random access memory (F-RAM) cell by turning on a first transistor having a first source-drain (SD) terminal coupled to the SN and a second SD terminal coupled to a bit-line (BL);
generating a data voltage on the BL by applying a data pulse having a peak voltage of V 1 to a plateline of a ferro-capacitor coupled between the plateline and the SN;
decoupling the BL from the SN by turning off the first transistor;
discharging the SN by turning on a second transistor having a first source-drain (SD) terminal coupled to the SN and a second SD terminal coupled to a reference bit-line (BLB); and
generating a reference voltage on the BLB derived from an unswitched (U-term) of the ferro-capacitor of the F-RAM cell by applying a reference pulse to the plateline and sweeping the voltage of the reference pulse from a voltage less than V 1 to a peak voltage of V 2 greater than V 1 ;
decoupling the BLB from the SN by turning off the second transistor; and
coupling the data voltage on the BL and the reference voltage on the BLB to a sense amplifier (SA) to read data stored in the F-RAM cell,
wherein applying the reference pulse to the plateline further serves as a clear pulse to harden the U-term in the ferro-capacitor.
11. The method of claim 10 , further comprising coupling the BL to a bit-line pre-charge circuit and pre-charging the BL to a predetermined voltage prior to discharging the SN.
12. The method of claim 11 , wherein discharging the SN comprises discharging the SN through the bit-line pre-charge circuit.
13. The method of claim 12 further comprising decoupling the BL from the bit-line pre-charge circuit prior to applying the data pulse and wherein the bit-line pre-charge circuit remains electrically decoupled from the bit-line during a time between the data pulse and the reference pulse.
14. The method of claim 10 , wherein a bit-line capacitance is substantially equal to a reference bit-line capacitance.
15. The method of claim 10 , wherein a bit-line capacitance is greater than a reference bit-line capacitance.
16. A method comprising:
discharging a storage node (SN) of a ferroelectric random access memory (F-RAM) cell by turning on a first transistor having a first source-drain (SD) terminal coupled to the SN and a second SD terminal coupled to a bit-line (BL);
generating a data voltage on the BL by applying a first voltage pulse having a peak voltage of V 1 to a plateline of a ferro-capacitor coupled between the plateline and the SN;
decoupling the BL from the SN by turning off the first transistor;
discharging the SN by turning on a second transistor having a first source-drain (SD) terminal coupled to the SN and a second SD terminal coupled to a reference bit-line (BLB); and
generating a reference voltage on the BLB derived from an unswitched (U-term) of the ferro-capacitor of the F-RAM cell by applying a second voltage pulse to the plateline and sweeping the voltage of the second voltage pulse from a voltage less than V 1 to a peak voltage of V 2 greater than V 1 , while concurrently coupling the data voltage on the BL and the reference voltage on the BLB to a sense amplifier (SA) to read data stored in the F-RAM cell.
17. The method claim 16 , wherein applying the second voltage pulse further serves as a clear pulse to harden the U-term in the ferro-capacitor.
18. The method of claim 16 , further comprising coupling the BL to a bit-line pre-charge circuit and pre-charging the BL to a predetermined voltage prior to discharging the SN.
19. The method of claim 18 , wherein discharging the SN comprises discharging the SN through the bit-line pre-charge circuit.
20. The method of claim 19 further comprising decoupling the BL from the bit-line pre-charge circuit prior to applying the data pulse and wherein the bit-line pre-charge circuit remains electrically decoupled from the bit-line during a time between the data pulse and the reference pulse.