IP Library Granted Patent US 10,643,514
Granted Patent B2
US 10,643,514 · App. 16/058,557 · Granted May 5, 2020

Display device with inspection transistor and method for inspecting display device

Inventors: Hiroaki Goto (Osaka, JP); Masafumi Hirata (Hyogo, JP)
Assignee: Panasonic Liquid Crystal Display Co., Ltd.
G09G3/006G02F1/1309G02F1/1368G02F1/136286G09G3/20G09G3/36H01L27/124H01L27/1214H01L27/1255G02F2001/136254G09G2330/12
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Quick Facts
Patent No.
US 10,643,514
App. No.
16/058,557
Granted
May 5, 2020
Kind
B2
Abstract

A display device comprises: inspection transistors electrically connected to signal lines respectively; an inspection wiring through which an inspection signal is supplied to the inspection transistors; and an abnormality determination unit that determines whether the display panel is abnormal. The signal line is electrically connected to a gate electrode of the inspection transistor, and the abnormality determination unit determines whether the display panel is abnormal based on a voltage level of the inspection signal outputted from a source electrode of the inspection transistor.

Claims (36)

1. A display device comprising:

a plurality of signal lines arranged in a display region of a display panel;

a plurality of inspection transistors each of which has a drain electrodes, a source electrode and a gate electrode electrically connected to a corresponding one of the plurality of signal lines;

an inspection wiring through which an inspection signal is supplied to the drain electrodes of the plurality of inspection transistors, the inspection wiring including a first inspection wiring and a second inspection wiring; and

an abnormality determination unit that are electrically connected to at least one of the source electrodes of the plurality of inspection transistors and determines whether the display panel is abnormal,

wherein the abnormality determination unit determines whether the display panel is abnormal based on a voltage level of the inspection signal outputted from the at least one of the source electrodes of the plurality of inspection transistors,

the plurality of signal lines are divided into at least a first group including a part of the plurality of signal lines immediately adjacent to each other and a second group including a part of the plurality of signal lines immediately adjacent to each other,

a part of the plurality of inspection transistors have control electrodes respectively and electrically connected to the plurality of signal lines included in the first group, are connected in cascade, and are electrically connected to the first inspection wiring, and

another part of the plurality of inspection transistors have control electrodes respectively and electrically connected to the plurality of signal lines included in the second group, are connected in cascade, and are electrically connected to the second inspection wiring.

2. The display device according to claim 1 , wherein

the plurality of signal lines are a plurality of data lines through which image data is supplied to each pixel,

in each of two inspection transistors immediately adjacent to each other in the first group, respective gate electrodes are electrically connected to different data lines, and the source electrode of one of the inspection transistors and the drain electrode of the other inspection transistor are electrically connected to each other, and

in each of two inspection transistors immediately adjacent to each other in the second group, respective gate electrodes are electrically connected to different data lines, and the source electrode of one of the inspection transistors and the drain electrode of the other inspection transistor are electrically connected to each other.

3. The display device according to claim 1 , wherein

the plurality of signal lines are a plurality of gate lines through which a gate signal is supplied to a transistor of each pixel.

4. A display device comprising:

a plurality of gate lines arranged in a display area of a display panel;

a plurality of first inspection transistors, each of which has a drain electrode, a source electrode and a gate electrode electrically connected to a corresponding one of the plurality of gate lines;

a plurality of second inspection transistors, each of which has a drain electrode, a source electrode and a gate electrode electrically connected to a corresponding one of the source electrodes of the plurality of first inspection transistors;

a plurality of capacitors, each of which has a first electrode electrically connected to a corresponding one of the source electrodes of the plurality of first inspection transistors and a corresponding one of the gate electrodes of the plurality of second inspection transistors;

an inspection wiring through which an inspection signal is supplied to the drain electrodes of the plurality of first inspection transistors and the drain electrodes of the plurality of second inspection transistors; and

an abnormality determination unit electrically connected to at least one of the source electrodes of the plurality of second inspection transistors and that determines whether the display panel is abnormal, wherein

the abnormality determination unit determines whether the display panel is abnormal based on a voltage level of the inspection signal outputted from the at least one of the source electrodes of the plurality of second inspection transistors.

5. The display device according to claim 4 , further comprising a reset line electrically connected to second electrodes of the plurality of capacitors, a reset signal being supplied through the reset line in order to discharge the plurality of capacitors.

6. A method for inspecting a display device,

the display device including:

a plurality of gate lines arranged in a display area of the display panel;

a plurality of first inspection transistors each of which has a drain electrode, a source electrode and a gate electrode electrically connected to a corresponding one of the plurality of gate lines;

a plurality of second inspection transistors each of which has a drain electrode, a source electrode and a gate electrode electrically connected to a corresponding one of the source electrodes of the plurality of first inspection transistors;

a plurality of capacitors each of which has a first electrode electrically connected to a corresponding one of the source electrodes of the plurality of first inspection transistors and a corresponding one of the gate electrodes of the plurality of second inspection transistors; and

an inspection wiring through which an inspection signal is supplied to the drain electrodes of the plurality of first inspection transistors and the drain electrodes of the plurality of second inspection transistors,

the method comprising the steps of:

supplying sequentially a gate signal to the plurality of gate lines in a writing period and supplying the inspection signal having a voltage level bringing the plurality of second inspection transistors into an on state to the drain electrodes of the plurality of first inspection transistors through the inspection wiring in the writing period;

supplying the inspection signal to the drain electrodes of the plurality of second inspection transistors through the inspection wiring in a vertical flyback period; and

determining whether the display panel is abnormal based on a voltage level of the inspection signal outputted from at least one of the source electrode of the second inspection transistor.

7. The method according to claim 6 , further comprising the step of supplying a reset signal to second electrodes of the capacitors through a reset line after determining whether the display panel is abnormal in the vertical flyback period.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2023
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 064292/0775 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2018
From: GOTO, HIROAKI; HIRATA, MASAFUMI
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 047188/0183 →
Priority Claims (1)
JP 2016-037777 · Feb 29, 2016 · national
Continuity (2)
Continuation PCTJP2017005336 · Feb 14, 2017
Related Publication 20180350285A1 · Dec 6, 2018