Systems and methods for dynamic random access memory (DRAM) cell voltage boosting
A memory device is provided. The memory device includes a memory array having at least one memory cell. The memory device further includes a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof. The memory device additionally includes a first bus configured to provide a first electric power to the sense amplifier circuit, and a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell.
1. A memory device, comprising:
a memory array having at least one memory cell;
a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof;
a first bus configured to provide a first electric power to the sense amplifier circuit; and
a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell, wherein the first bus is electrically coupled to a first power supply, wherein the second bus is electrically coupled to a second power supply, and wherein the second power supply is configured to deliver a voltage higher than the first power supply.
2. The memory device of claim 1 , wherein the first electric power comprises a first inherent capacitance power of the first bus, wherein the second electric power comprises a second inherent capacitance power of the second bus, or a combination thereof.
3. The memory device of claim 1 , wherein the second circuit comprises a wordline driver circuit configured to provide the second electric power to a wordline of the memory array, and wherein the wordline is electrically coupled to the at least one memory cell.
4. The memory device of claim 1 , wherein the sense amplifier circuit comprises a P-sense amplification circuit having one or more P-type devices coupled via a cross-junction, wherein the P-sense amplification circuit is electrically coupled to the at least one memory cell.
5. The memory device of claim 1 , wherein the first power supply comprises a VCC power supply delivering between 0.5 to 1.5 volts DC and wherein the second power supply comprises a VCCP power supply delivering between 2 to 5 volts DC.
6. The memory device of claim 1 , comprising a global wordline circuit, wherein the global wordline circuit is configured to electrically couple the first bus with the second bus after receipt of a precharge (PRE) command to provide for the first electric power and the second electric power to the at least one memory cell.
7. The memory device of claim 6 , wherein the global wordline circuit is configured to disconnect the first bus from a first power supply, disconnect the second bus from a second power supply, and subsequently to electrically couple the first bus with the second bus.
8. The memory device of claim 7 , wherein the global wordline circuit comprises a P-type device electrically coupling the first bus to the second bus and wherein the global wordline circuit is configured to electrically couple the first bus with the second bus via actuation of the P-type device.
9. A method for charging a memory cell included in a memory array, comprising:
receiving a precharge (PRE) command;
electrically coupling a first bus to a second bus;
charging the memory cell via a first electric power provided by the first bus and via a second electric power provided by the second bus;
turning off a wordline included in the memory array, wherein the wordline is electrically coupled to the memory cell; and
writing a 1's data into the memory cell prior to receiving the PRE command.
10. The method of claim 9 , wherein the first electric power comprises a first inherent capacitance power of the first bus, wherein the second electric power comprises a second inherent capacitance power of the second bus, or a combination thereof.
11. The method of claim 9 , wherein writing the 1's data into the memory cell comprises using a sense amplifier circuit to write the 1's data.
12. The method of claim 11 , comprising turning off the sense amplifier circuit after turning off the wordline.
13. The method of claim 9 , wherein electrically coupling the first bus to the second bus comprises actuating a single P-type device included in a global wordline circuit to electrically couple the first bus to the second bus.