III-nitride high electron mobility transistor
View Patent ↗An III-nitride HEMT, including a substrate; a semiconductor epitaxial stack, formed on the substrate, including a buffer structure, a channel layer formed on the buffer structure and a barrier layer formed on the channel layer, wherein a two-dimensional electron gas is formed between the channel layer and the barrier layer; and a first electrode, a third electrode and a second electrode located in between, respectively formed on the barrier layer, wherein the semiconductor epitaxial stack includes a sheet resistance greater than 500 Ω/sq, wherein there is a first minimum space between the first electrode and the second electrode, a second minimum space between the second electrode and the third electrode, and the ratio of the first minimum space to the sum of first minimum space and the second minimum space is between 0.77 and 1, wherein the second electrode includes a length greater than or equal to 9 μm.
1. A III-nitride high electron mobility transistor (HEMT), comprising:
a substrate;
a semiconductor epitaxial stack, formed on the substrate, comprising:
a buffer structure;
a channel layer, formed on the buffer structure; and
a barrier layer, formed on the channel layer, wherein a two-dimensional electron gas is formed between the channel layer and the barrier layer; and
a first electrode, a second electrode and a third electrode, respectively formed on the barrier layer, wherein the second electrode is located between the first electrode and the third electrode,
wherein the semiconductor epitaxial stack comprises a sheet resistance greater than 500 Ω/sq,
wherein there is a first minimum space between the first electrode and the second electrode, a second minimum space between the second electrode and the third electrode, and the first minimum space and the sum of the first minimum space and the second minimum space comprises a ratio greater than or equal to 0.77 and less than 1,
wherein the second electrode comprises a length greater than or equal to 9 μm.
2. The III-nitride HEMT of claim 1 , wherein the second minimum space is greater than or equal to 20 μm.
3. The III-nitride HEMT of claim 1 , wherein the HEMT comprises a saturation voltage less than 6.5 volts.
4. The III-nitride HEMT of claim 1 , wherein the HEMT comprises a breakdown voltage greater than 500 volts.
5. The III-nitride HEMT of claim 1 , wherein the III-nitride HEMT is a normally-on III-nitride HEMT.
6. The III-nitride HEMT of claim 1 , wherein from a top view, the second electrode comprises at least two ends, and the at least two ends comprise a straight line and a hollow closed area.
7. The III-nitride HEMT of claim 6 , wherein from the top view, the third electrode is located at the hollow closed area.
8. The III-nitride HEMT of claim 1 , wherein the buffer structure comprises a super-lattice stack, and wherein the buffer structure is closer to the substrate than the channel layer, and the buffer structure comprises a higher sheet resistance than the channel layer does.
9. The III-nitride HEMT of claim 8 , wherein the semiconductor epitaxial stack comprises a back barrier layer between the buffer structure and the channel layer.
10. The III-nitride HEMT of claim 9 , wherein the back barrier layer comprises a thickness less than 50 nm.