Transistor display panel including transistor having auxiliary layer overlapping edge of gate electrode
View Patent ↗A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.
1. A transistor display panel comprising:
a substrate;
a gate line disposed on the substrate and extending in a first direction;
a gate electrode protruding from the gate line;
a gate insulating layer disposed on the gate line and the gate electrode;
a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other;
a data line disposed on the gate insulating layer and extending in a second direction crossing the first direction;
a drain electrode disposed on the gate insulating layer and the semiconductor layer, and spaced apart from the data line; and
a pixel electrode connected to the drain electrode,
wherein:
the auxiliary layer overlaps an edge of the gate electrode and does not overlap the semiconductor layer in a plan view; and
the semiconductor layer includes a channel overlapping the gate electrode.
2. The transistor display panel of claim 1 , wherein the semiconductor layer and the auxiliary layer comprise amorphous silicon.
3. The transistor display panel of claim 2 , wherein:
the data line comprises a source electrode extending toward the gate electrode; and
the source electrode is disposed on the gate insulating layer and the semiconductor layer.
4. The transistor display panel of claim 3 , wherein:
the gate electrode has a first edge, a second edge, and a third edge facing the second edge;
a portion of the first edge overlaps the drain electrode in a plan view; and
a portion of the second edge overlaps the source electrode in a plan view.
5. The transistor display panel of claim 4 , wherein the auxiliary layer overlaps at least one of the first edge, the second edge, and the third edge of the gate electrode in a plan view.
6. The transistor display panel of claim 5 , wherein the auxiliary layer comprises a first auxiliary layer overlapping the drain electrode in a plan view.
7. The transistor display panel of claim 6 , wherein the first auxiliary layer is disposed between the first edge and the drain electrode.
8. The transistor display panel of claim 7 , wherein:
the auxiliary layer further comprises a second auxiliary layer spaced apart from the first auxiliary layer; and
the second auxiliary layer overlaps the source electrode in a plan view.
9. The transistor display panel of claim 8 , wherein the second auxiliary layer is disposed between the second edge of the gate electrode and the source electrode.
10. The transistor display panel of claim 5 , wherein the auxiliary layer overlaps the first edge, the second edge, and the third edge of the gate electrode in a plan view.
11. The transistor display panel of claim 10 , wherein the auxiliary layer overlaps the source electrode and the drain electrode in a plan view.
12. A transistor display panel comprising:
a substrate;
a gate line disposed on the substrate and extending in a first direction;
a gate electrode protruding from the gate line;
a gate insulating layer disposed on the gate line and the gate electrode;
a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other;
a data line disposed on the semiconductor layer and extending in a second direction crossing the first direction;
a source electrode disposed on the semiconductor layer and extending from the data line toward the gate electrode;
a drain electrode disposed on the semiconductor layer and spaced apart from the source electrode; and
a pixel electrode connected to the drain electrode,
wherein:
the auxiliary layer overlaps an edge of the gate electrode and does not overlap the semiconductor layer in a plan view; and
the semiconductor layer includes a channel overlapping the gate electrode.
13. The transistor display panel of claim 12 , wherein the semiconductor layer and the auxiliary layer comprise amorphous silicon.
14. The transistor display panel of claim 13 , wherein:
the gate electrode has a first edge, a second edge, and a third edge facing the second edge;
a portion of the first edge overlaps the drain electrode in a plan view;
a portion of the second edge overlaps the source electrode in a plan view.
15. The transistor display panel of claim 14 , wherein the auxiliary layer overlaps the first edge, the second edge, and the third edge of the gate electrode.