Multiple endianness compatibility

1. A method, comprising:

receiving a plurality of bytes in a particular endianness format; and

responsive to the particular endianness format being a first endianness format:

reordering, in memory using sensing circuitry, bits of each byte of the plurality of bytes on a bytewise basis, wherein:

an order of the bits, with respect to more than one byte:

is non-sequential prior to the reordering; and

is sequential subsequent to the reordering;

storing the reordered plurality of bytes in an array of memory cells of the memory; and

adjusting a shift direction associated with performing a number of operations on the plurality of bytes stored in the array.

2. The method of claim 1 , further comprising, responsive to the particular endianness format being a second endianness format, storing the plurality of bytes in the array without reordering bits of the plurality of bytes.

3. The method of claim 1 , further comprising receiving the plurality of bytes from a host and setting a state of a flag based on an endianness corresponding to the host.

4. The method of claim 1 , wherein reordering the bits in each byte of the plurality of bytes comprises ordering bits of each byte from a bitwise big endian format to a bitwise little endian format.

5. The method of claim 1 , comprising performing a number of shift operations on the bits in each byte of the plurality of bytes.

6. The method of claim 5 , wherein the bits are shifted in a more significant bit direction.

7. The method of claim 5 , wherein the bits in each byte of the plurality of bytes are shifted:

in a rightward direction when the plurality of bytes are in the first endianness format; and

in a leftward direction when the plurality of bytes are in a second endianness format.

8. The method of claim 5 , wherein:

each of the bits is stored in one of a respective number of compute components; and

performing the number of shift operations comprises shifting each of the number of bits from a compute component coupled to a memory cell storing a lesser significant bit to a compute component coupled to a memory cell storing a more significant bit.

9. The method of claim 1 , comprising, responsive to receiving the plurality of bytes in the first endianness format, reversing an order of row addresses received from a sequencer when bytes are stored in rows.

10. The method of claim 1 , comprising, responsive to receiving the plurality of bytes in the first endianness format, reversing an order of column addresses received from a sequencer when bytes are stored in columns.

11. The method of claim 1 , comprising sending the reordered bits to a controller.

12. A method, comprising:

determining a status of a flag indicating an endianness of a plurality of bytes;

in response to a flag being set, indicating the plurality of bytes is received in a first endianness format:

changing a direction of shifting operations performed in an array of memory cells;

on a bytewise basis, reversing, via a memory controller using sensing circuitry, an order of bits of the plurality of bytes stored in a group of memory cells, wherein:

an order of the bits, with respect to more than one byte:

is non-sequential prior to the reordering; and

is sequential subsequent to the reordering;

reversing an order of addresses on a bytewise basis; and

providing the bits with the reversed order and the corresponding addresses with reversed order to a host.

13. The method of claim 12 , further comprising, in response to the flag not being set based on the plurality of bytes being received in a second endianness format, providing the bits of the plurality of bytes stored in the group of memory cells to the host.

14. The method of claim 12 , wherein:

the first endianness format is a bytewise little endian format; and

the second endianness format is a bytewise big endian format.

15. The method of claim 12 , wherein changing the direction of shifting operations performed in the array comprises:

changing from shifting left to shifting right when the bits are stored in rows; and

changing from shifting up to shifting down when the bites are stored in columns.

16. An apparatus comprising:

a controller coupled to an array of memory cells, wherein the controller is configured to:

receive bits of a plurality of bytes, wherein:

a flag is set responsive to the bits being in a first endian format; and

the flag is not set responsive to the bits being in a second endian format; and

responsive to the flag being set, reorder, in memory using sensing circuitry, the received bits from the first endian format to the second endian format by reversing the bits in each byte as each byte is received, wherein:

an order of the bits, with respect to more than one byte:

is non-sequential prior to the reordering; and

is sequential subsequent to the reordering.

17. The apparatus of claim 16 , wherein the controller is further configured to reverse an order of the addresses associated with the plurality of bytes in response to the flag being set.

18. The apparatus of claim 16 , wherein the array receives the bits and stores the bits:

independent of altering an ordering of the bits and addresses associated with the bits in response to the flag not being set; and

after the reordering of the bits and reversing an order of the addresses when the flag is set.

19. The apparatus of claim 16 , comprising an array of memory cells configured to perform a number of shift operations in a particular direction based on whether the flag is set.

20. The apparatus of claim 16 , wherein the array performs a number of operations independent of being aware of which endianness format a host in communication with the array uses.