Accelerating neural networks in hardware using interconnected crossbars

1. A computing unit for accelerating a neural network, comprising:

an input unit that includes a digital-to-analog conversion unit that is configured to receive a digital input vector and convert the digital input vector into a first analog signal that is provided as an input to a first interconnected analog crossbar circuit of a plurality of analog crossbar circuits;

an output unit that includes an analog-to-digital conversion unit that is configured to receive as an input a second analog signal from the output of a last interconnected analog crossbar circuit of a plurality of analog crossbar circuits and convert the second analog signal into a digital output vector; and

a plurality of interconnected analog crossbar circuits that include the first interconnected analog crossbar circuit and the last interconnected crossbar circuits, wherein each interconnected analog crossbar circuit of the plurality of interconnected analog crossbar circuits corresponds to a particular layer of the neural network, wherein each interconnected analog crossbar circuit includes a plurality of crosspoints, wherein each crosspoint stores a weight of a plurality of weights associated with a layer of the neural network to which the interconnected analog crossbar circuit corresponds,

wherein one or more of the interconnected analog crossbar circuits is configured to receive as an input a third analog signal from another interconnected analog crossbar circuit of the plurality of interconnected crossbar circuits and perform one or more operations on the third analog signal based on the matrix weights stored by the crosspoints of the interconnected analog crossbar circuit that received the third analog signal to generate an output analog signal, and

wherein the computing unit does not include any other analog-to-digital conversion units that generate a digital output based on an input that includes an analog signal output by an interconnected analog crossbar circuit other than the analog-to-digital conversion unit of the output unit.

2. The circuit of claim 1 , wherein the one or more operations include performing matrix multiplication operations on the third analog signal based on the matrix weights stored by the crosspoints of the interconnected analog crossbar circuit that received the third analog signal to generate an output analog signal.

3. The computing unit of claim 1 , wherein the neural network is a fully-connected neural network.

4. The circuit of claim 1 , wherein the computing unit does not include any other digital-to-analog conversion units that generate an analog output based on a digital vector for input to an interconnected analog crossbar circuit other than the digital-to-analog conversion unit of the input unit.

5. The computing unit of claim 1 , wherein each crossbar circuit of the plurality of interconnected analog crossbar circuits other than the first crossbar circuit is configured to receive as input an analog output generated by a previous analog crossbar circuit.

6. The computing unit of claim 1 , further comprising:

at least one array of analog signal amplifiers that is positioned between a pair of analog crossbar circuits included in the plurality of interconnected analog crossbar circuits.

7. The computing unit of claim 6 , wherein the at least one array of analog signal amplifiers is configured to (i) receive as an input an analog output generated by the second analog crossbar circuit and (ii) generate as an output an analog output for use as an input to a fourth analog crossbar circuit.

8. The computing unit of claim 6 , wherein each crossbar circuit of the plurality of interconnected analog crossbar circuits other than the first crossbar circuit is configured to receive as an input (i) an analog output generated by a previous analog crossbar circuit or (ii) an analog output generated by the at least one array of analog signal amplifiers.