Apparatuses and methods for performing multiple memory operations
View Patent ↗The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.
1. A memory device comprising:
a memory array comprising memory cells;
a memory controller connected to the memory array and configured to:
receive a single command identifying a first program command and a second program command; and
cause, in response to the single command, the first program command, a first verify operation, and the second program command to be performed on the memory array.
2. The memory device of claim 1 , wherein the first verify operation is performed after the first program command is performed and before the second program command is performed.
3. The memory device of claim 1 , wherein the memory controller is further configured to:
cause, in response to the single command, a second verify operation to be performed on the memory array after the second program command is performed.
4. The memory device of claim 1 , wherein the memory controller is further configured to cause the first program command to be performed by:
causing a target memory cell of the memory cells to be selected; and
causing a program pulse to be applied to the target memory cell.
5. The memory device of claim 4 , wherein the memory controller is further configured to:
determine whether the target memory cell has reached a threshold resistance based at least in part on the first verify operation.
6. The memory device of claim 5 , wherein the memory controller is further configured to:
cause, in response to a determination that the target memory cell has not reached the threshold resistance, one or more additional program pulses to be applied to the target memory cell.
7. The memory device of claim 4 , wherein the memory controller is further configured to cause the first verify operation to be performed by causing a program verification pulse to be applied to the target memory cell.
8. The memory device of claim 7 , wherein the memory controller is further configured to:
cause the target memory cell to be selected by causing a selection voltage to be applied to a word line associated with the target memory cell; and
cause the first verify operation to be performed by causing the program verification pulse to be applied to the word line and causing a current through the target memory cell to be sensed based at least in part on the program verification pulse.
9. The memory device of claim 4 , wherein the memory controller is further configured to cause the second program command to be performed by:
causing a second target memory cell of the memory cells to be selected; and
causing one or more program pulses to be applied to the second target memory cell, wherein the second target memory cell is different than the target memory cell.
10. A method, comprising:
receiving, by a memory controller, a single command comprising:
a first operation descriptor comprising a first operation type and a first address; and
a second operation descriptor comprising a second operation type and a second address different than the first address; and
performing, based at least in part on receiving the single command, a first memory access operation of the first operation type on a first memory cell that is associated with the first address and a second memory access operation of the second operation type on a second memory cell that is associated with the second address.
11. The method of claim 10 , wherein:
the single command further comprises an indication of an execution order; and
the first memory access operation and the second memory access operation are performed based at least in part on the execution order.
12. The method of claim 10 , wherein the first operation descriptor comprises a first data length and first data of the first data length, the method further comprising:
transferring, by the memory controller, the first data to a memory device comprising the first memory cell and the second memory cell based at least in part on the first data length and the first data.
13. The method of claim 12 , wherein the single command comprises a first tag that identifies the first operation descriptor, the method further comprising:
transferring, by the memory controller, the first data to the memory device based at least in part on the first tag.
14. The method of claim 10 , wherein:
the first operation descriptor comprises a first descriptor length that specifies a first length of the first operation descriptor, and
the second operation descriptor comprises a second descriptor length that specifies a second length of the second operation descriptor.
15. The method of claim 10 , wherein the first memory access operation is different than the second memory access operation.
16. A memory device comprising:
a memory array comprising memory cells;
a memory controller connected to the memory array and configured to:
receive a single command that comprises a first operation descriptor comprising a first operation type and a first address, and a second operation descriptor comprising a second operation type and a second address different than the first address; and
cause, based at least in part on receiving the single command, a first memory access operation of the first operation type to be performed on a first memory cell that is associated with the first address and a second memory access operation of the second operation type to be performed on a second memory cell that is associated with the second address.
17. The memory device of claim 16 , wherein:
the single command further comprises an indication of an execution order; and
the memory controller is configured to cause the first memory access operation and the second memory access operation to be performed in an order based on the execution order.
18. The memory device of claim 16 , wherein:
the first operation descriptor comprises a first data length and first data having the first data length; and
the memory controller is further configured to transfer the first data to the memory device based at least in part on the first data length and the first data.
19. The memory device of claim 18 , wherein:
the single command comprises a first tag that identifies the first operation descriptor; and
the memory controller is further configured to transfer the first data to the memory device further based at least in part on the first tag.
20. The memory device of claim 16 , wherein:
the first operation descriptor comprises a first descriptor length that specifies a first length of the first operation descriptor, and
the second operation descriptor comprises a second descriptor length that specifies a second length of the second operation descriptor.