IP Library Granted Patent US 10,990,468
Granted Patent B2
US 10,990,468 · App. 16/067,825 · Granted Apr 27, 2021

Computing system and error handling method for computing system

Inventors: Akihiko Araki (Tokyo, JP); Masakuni Agetsuma (Tokyo, JP); Sachie Tajima (Tokyo, JP); Takanobu Suzuki (Tokyo, JP); Masanori Takada (Tokyo, JP)
Assignee: HITACHI, LTD.
G06F11/0793G06F11/0706G06F11/079G06F11/0772G06F11/0787G06F11/142G06F12/00G06F11/2038G06F11/2048
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Quick Facts
Patent No.
US 10,990,468
App. No.
16/067,825
Granted
Apr 27, 2021
Kind
B2
Abstract

A computing system that can maintain reliability required of a storage program while causing the storage program to operate on an operating system (OS) is provided. A processor of the computing system executes an OS controlling a hardware device and a storage program operating on the OS and using the hardware device via the OS. The OS identifies an error status of the hardware device when receiving a notification of an error that has occurred to the hardware device, and notifies the storage program that operates on the OS of the error status when the error status satisfies a predetermined condition. The storage program determines error handling on the hardware device on the basis of the error status, and requests the OS to perform the determined error handling. The OS performs the determined error handling on the hardware device.

Claims (50)

1. A computing system comprising:

a processor that executes an operating system controlling a hardware device and a storage program operating on the operating system and using the hardware device via the operating system; and

a memory that records condition management information managing a predetermined condition on which the storage program determines error handling on the hardware device,

wherein upon the operating system receiving a notification of an error that occurred in the hardware device, the operating system determines to execute a recovery processing to the hardware device and executes the recovery processing to the hardware device,

wherein the storage program sets an interrupt handler in the operating system,

wherein the interrupt handler identifies an error status of the hardware device and upon determining the error status satisfies a predetermined condition, the operating system notifies the error status to the storage program running on the operating system without performing the recovery processing,

wherein the storage program that receives a notice of the error status requests the operating system to perform hardware device processing,

wherein the operating system performs to shutdown processing of the hardware device,

wherein the memory has a queue that manages processes planned to be executed by the operating system,

wherein the operating system has, as interrupt handlers, a first interrupt handler and a second interrupt handler added in response to a request from the storage program,

wherein the processor executes the first interrupt handler when receiving an interrupt as the notification of the error,

wherein the first interrupt handler registers error handling by the operating system in the queue,

wherein the processor executes the second interrupt handler after executing the first interrupt handler, and

wherein the second interrupt handler determines whether the error status satisfies the predetermined condition while referring to the condition management information, and cancels the error handling by the operating system registered in the queue when the error status satisfies the predetermined condition.

2. The computing system according to claim 1 , wherein

the condition management information manager, as the predetermined condition, a threshold for a number of occurrences of errors for every error type of the error that has occurred to the hardware device.

3. The computing system according to claim 1 , wherein

the error status satisfies the predetermined condition at a time of occurrence of an Uncorrectable and Fatal error to the hardware device used in an I/O process executed by the storage program, and

the error handling determined by the storage program is the blocking process on the hardware device used in the I/O process.

4. The computing system according to claim 1 , wherein

the storage program stops using the hardware device in an I/O process by the storage program after determining a blocking process as the error handling on the hardware device, and

the operating system executes the blocking process on the hardware device after the storage program stops using the hardware device.

5. The computing system according to claim 1 , wherein

when the storage program determines the error handling on the hardware device, and

when the operating system executes the error handling determined by the storage program on the hardware device,

the storage program records an error log.

6. An error handling method for a computing system that executes an operating system controlling a hardware device and a storage program operating on the operating system and using the hardware device via the operating system, wherein

the computing system includes a memory that has a first memory area referred to by the operating system and a second memory area referred to by the storage program, has a queue that manages processes planned to be executed by the operating system, and manages a predetermined condition on which the storage program determines error handling on the hardware device, and

the operating system has, as interrupt handlers, a first interrupt handler and a second interrupt handler added in response to a request from the storage program,

the error handling method comprising:

causing the first interrupt handler of the operating system to identify an error status of the hardware device when the first interrupt handler receives a notification of an error that has occurred to the hardware device, and to register error handling by the operating system in the queue when the error status satisfies the predetermined condition;

causing the first interrupt handler to store information about the hardware device to which the error has occurred and about an error content in the first memory area as error occurrence information identified as at least part of the error status;

causing the second interrupt handler added in response to the request from the storage program to determine whether the error status satisfies the predetermined condition after the first interrupt handler registers the error handling by the operating system in the queue, and to cancel the error handling by the operating system registered in the queue when the error status satisfies the predetermined condition;

causing the second interrupt handler to acquire the error occurrence information while referring to the first memory area, to store the error occurrence information in the second memory area referred to by the storage program, and to delete the error occurrence information in the first memory area;

causing the storage program to determine the error handling on the hardware device on the basis of the error occurrence information in the second memory area and requests the operating system to perform the determined error handling; and

causing the operating system to perform the determined error handling on the hardware device.

7. The computing system according to claim 1 , wherein

the memory has a first memory area referred to by the operating system and a second memory area referred to by the storage program,

the first interrupt handler of the operating system identifies the hardware device to which the error has occurred and an error content, and stores the identified hardware device and the identified error content in the first memory area as error occurrence information,

the second interrupt handler added in response to the request from the storage program acquires the error occurrence information while referring to the first memory area, stores the error occurrence information in the second memory area referred to by the storage program, and deletes the error occurrence information in the first memory area, and

the storage program determines the error handling on the hardware device on the basis of the error occurrence information in the second memory area.

8. The computing system according to claim 7 , wherein

the storage program identifies the hardware device to which the error has occurred while referring to the error occurrence information in the second memory area, and suspends an I/O process using the identified hardware device.

9. The computing system according to claim 8 , wherein

the storage program abandons a request of the I/O process using the identified hardware device when suspending the I/O process.

10. The computing system according to claim 9 , wherein

the storage program,

as a process for requesting the operating system to add the second interrupt handler to the operating system,

acquires information about the first interrupt handler that is the interrupt handler executed when the processor receives, from the operating system, an interrupt as the notification of the error, and

requests the operating system to add the second interrupt handler to the operating system so that the second interrupt handler is executed subsequently to execution of the first interrupt handler.

Assignments (2)
COMPANY SPLIT Recorded Aug 20, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069518/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2018
From: ARAKI, AKIHIKO; AGETSUMA, MASAKUNI; TAJIMA, SACHIE; SUZUKI, TAKANOBU; TAKADA, MASANORI
To: HITACHI, LTD.
Reel/Frame 046256/0730 →
Continuity (1)
Related Publication 20190026179A1 · Jan 24, 2019