Software-enhanced stateful switching architecture

1. A stateful network packet processing system, comprising:

a first stateful stage including a first state table and a first finite state machine (“FSM”) table; and

a second stateful stage including a second state table and a second FSM table;

wherein the system is configured to perform a distribution operation that defines when a flow should be processed by either the first stateful stage or the second stateful stage or by a combination of the first stateful stage and the second stateful stage,

wherein at least one of the first FSM table or the second FSM table is extended with states and transitions that support the distribution operation,

wherein at least one of the first stateful stage or the second stateful stage is configured to execute an evaluation operation comprising executing the distribution operation, and

wherein the evaluation operation provides a criterion for moving a particular flow from one of the first stateful stage or the second stateful stage to a respective other stateful stage of the first stateful stage or the second stateful stage,

wherein the first stateful stage and the second stateful stage are included in a software-defined networking (“SDN”) switch,

wherein the first stateful stage is implemented in hardware as a hardware stateful stage and wherein the first state table is a hardware state table (“HST”) and wherein the first FSM table is a hardware FSM table (“HFSMT”),

wherein the second stateful stage is implemented in software as a software stateful stage and wherein the second state table is a software state table (“SST”) and wherein the second FSM table is a software FSM table (“SFSMT”)

wherein the evaluation operation translates an evaluation performed on flow and/or packet statistics into a binary variable,

wherein the software stateful stage is configured to execute the evaluation operation, and

wherein the evaluation operation comprises executing the distribution operation in a form of a one-way offloading scheme that triggers transitions from the software stateful stage to the hardware stateful stage based on the value of the binary variable.

2. The system according to claim 1 , wherein the hardware stateful stage is implemented as a Ternary Content-Addressable Memory (“TCAM”) memory-based stage.

3. The system according to claim 1 , wherein the software stateful stage is implemented as a combination of a general purpose processor with a dynamic random access memory (“DRAM”).

4. The system according to claim 1 , wherein each of the first stateful stage and the second stateful stage is configured to derive from a network packet's header a particular value that represents a key for the match fields of the state tables.

5. The system according to claim 4 , wherein each of the first stateful stage and the second stateful stage is further configured to pass the particular value together with information on a state associated to the network packet in the respective one of the first FSM table or the second FSM table to a respective one of the first state table or the second state table.

6. The system according to claim 1 , wherein the evaluation operation translates an evaluation performed on flow and/or packet statistics into a binary variable.

7. The system according to claim 1 , wherein the first stateful stage and the second stateful stage are implemented by using two physically separated data paths that are linked with each other by an external connection.

8. The system according to claim 1 , comprising one or more supplemental stateful stages in addition to the first stateful stage and the second stateful stage.

9. A stateful network packet processing system, comprising:

a first stateful stage including a first state table and a first finite state machine (“FSM”) table; and

a second stateful stage including a second state table and a second FSM table;

wherein the system is configured to perform a distribution operation that defines when a flow should be processed by either the first stateful stage or the second stateful stage or by a combination of the first stateful stage and the second stateful stage,

wherein at least one of the first FSM table or the second FSM table is extended with states and transitions that support the distribution operation,

wherein the first stateful stage is implemented in hardware as a hardware stateful stage and wherein the first state table is a hardware state table (“HST”) and wherein the first FSM table is a hardware FSM table (“HFSMT”),

wherein the second stateful stage is implemented in software as a software stateful stage and wherein the second state table is a software state table (“SST”) and wherein the second FSM table is a software FSM table (“SFSMT”), and

wherein the HST contains only a single low-priority entry with a wildcard match and a software indicating state as an associated state.

10. A stateful network packet processing system, comprising:

a first stateful stage including a first state table and a first finite state machine (“FSM”) table; and

a second stateful stage including a second state table and a second FSM table;

wherein the system is configured to perform a distribution operation that defines when a flow should be processed by either the first stateful stage or the second stateful stage or by a combination of the first stateful stage and the second stateful stage,

wherein at least one of the first FSM table or the second FSM table is extended with states and transitions that support the distribution operation,

wherein the first stateful stage is implemented in hardware as a hardware stateful stage and wherein the first state table is a hardware state table (“HST”) and wherein the first FSM table is a hardware FSM table (“HFSMT”),

wherein the second stateful stage is implemented in software as a software stateful stage and wherein the second state table is a software state table (“SST”) and wherein the second FSM table is a software FSM table (“SFSMT”), and

wherein the HFSMT contains an entry that is associated with the software indicating state and that specifies an action that redirects matching packets to the SST.

11. The system according to claim 10 , wherein the redirection of matching packets from the HFSMT to the SST is implemented by using dedicated OpenFlow instructions.