Semiconductor device
View Patent ↗To provide a semiconductor device capable of restricting the substrate bias effect of a high-side transistor while enhancing the heat radiation property of a low-side transistor. A high-side NMOS transistor 101 is formed in a region S 1 on the surface of a SOI substrate 30 . A trench 41 surrounds the high-side NMOS transistor 101 . SiO 2 (first insulator) embeds the trench 41 . A low-side NMOS transistor 102 is formed in a region S 2 on the surface of the SOI substrate 30 around the trench 41 . The side face Sf connecting the region S 2 forming the low-side NMOS transistor 102 therein and the backside of the SOI substrate 30 is exposed.
1. A semiconductor device comprising:
a semiconductor substrate;
a high-side transistor formed in a first region on the surface of the semiconductor substrate;
a trench surrounding the high-side transistor;
a first insulator embedding the trench; and
a low-side transistor formed in a second region on the surface of the semiconductor substrate around the trench,
wherein the side face connecting the second region forming the low-side transistor therein and the backside of the semiconductor substrate is exposed.
2. A semiconductor device comprising:
a semiconductor substrate;
a high-side transistor formed in a first region on the surface of the semiconductor substrate;
a trench surrounding the high-side transistor;
a first insulator embedding the trench; and
a low-side transistor formed in a second region on the surface of the semiconductor substrate around the trench,
wherein the total area of the second region forming the low-side transistor therein is larger than the total area of the first region forming the high-side transistor therein.
3. The semiconductor device according to claim 1 ,
wherein the low-side transistor is arranged to surround the trench.
4. The semiconductor device according to claim 1 ,
wherein the first region is quadrangular, and
the low-side transistors are formed in two region adjacent to a pair of opposite sides of the first region.
5. The semiconductor device according to claim 4 ,
wherein the widths of the two regions adjacent to the pair of opposite sides of the first region, respectively, are equal in a direction in which the first region and the second regions are arranged.
6. The semiconductor device according to claim 1 ,
wherein the high-side transistors are formed in at least two mutually-separated regions,
the trenches surround the regions forming the high-side transistors therein, respectively, and
the distance between the adjacent trenches is shorter than the distance between the trench and the end of the semiconductor substrate in a direction in which the regions forming the high-side transistors therein are arranged.
7. The semiconductor device according to claim 1 ,
wherein the semiconductor substrate is configured in which a support substrate, a second insulator, and a P-type semiconductor are laminated, and
the first insulator contacts with the second insulator.
8. The semiconductor device according to claim 1 ,
wherein the low-side transistor and the high-side transistor are NMOS transistors or IGBTs.
9. The semiconductor device according to claim 1 ,
wherein thermal destruction energy of the low-side transistor is higher than thermal destruction energy of the high-side transistor.
10. The semiconductor device according to claim 1 ,
wherein the low-side transistor and the high-side transistor have a breakdown voltage of 30 V or more.