IP Library Granted Patent US 10,615,953
Granted Patent B2
US 10,615,953 · App. 16/076,710 · Granted Apr 7, 2020

Apparatuses and methods for compensating phase fluctuations

Inventors: Uri Perlmutter (Holon, IL); Michael Kerner (Tel Mond, IL); Uri Parker (Shimshit, IL)
Assignee: Apple Inc.
H04L7/0016H03L7/0805H03L7/0814H03L7/093H04L7/0331H03L2207/50H04B1/123
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Quick Facts
Patent No.
US 10,615,953
App. No.
16/076,710
Granted
Apr 7, 2020
Kind
B2
Abstract

The present disclosure relates to methods and apparatuses for compensating carrier or clock signal phase fluctuations. An apparatus comprises a digital phase locked loop ( 210 ) comprising a phase error output ( 214 ) for a phase error ( 216 ) between a reference signal ( 218 ) and an output signal ( 212 ) generated by the digital phase locked loop, and a phase rotator ( 220 ) coupled to the phase error output ( 214 ) and configured to rotate a phase of a data signal based on the phase error ( 216 ).

Claims (38)

1. Apparatus for compensating phase fluctuations, comprising:

a digital phase locked loop comprising a phase error output for a phase error between a reference signal and an output signal generated by the digital phase locked loop;

filter circuitry coupled between the phase error output and a phase rotator and configured to separate the phase error from noise; and

the phase rotator coupled to the phase error output and configured to rotate a phase of a data signal based on the filtered phase error.

2. The apparatus of claim 1 , further comprising:

a signal combiner configured to combine the data signal with the output signal prior to or after rotating the phase of the data signal.

3. The apparatus of claim 1 , wherein the data signal a transmit signal.

4. The apparatus of claim 1 , wherein the data signal a receive signal.

5. The apparatus of claim 1 , wherein the data signal is a digital baseband signal.

6. The apparatus of claim 5 , wherein the digital baseband signal is a quadrature modulated signal or a polar modulated signal.

7. The apparatus of claim 5 , further comprising:

a signal combiner configured to combine a received RF signal with the output signal to generate the digital baseband signal.

8. The apparatus of claim 5 , further comprising:

a signal combiner configured to combine the digital baseband signal with the output signal to generate an RF transmit signal.

9. The apparatus of claim 1 , wherein the filter circuitry comprises a digital filter comprising filter coefficients based on phase error samples and/or phase error statistics.

10. The apparatus of claim 1 , wherein the filter circuitry comprises an adaptive digital filter comprising adaptive filter coefficients based on decision feedback.

11. The apparatus of claim 1 , wherein the filter circuitry comprises a non-causal filter.

12. The apparatus of claim 1 , wherein the filter circuitry comprises a low-pass filter.

13. The apparatus of claim 1 , wherein the filter circuitry comprises a linear filter, in particular a linear MMSE filter.

14. Transmitter circuitry, comprising:

a digital phase locked loop configured to generate a carrier signal and to determine a phase error between a reference signal and the carrier signal;

a digital non-causal linear filter coupled between the digital phase locked loop and a transmit data path and configured to generate smoothened phase error samples of the phase error; and

a phase rotator coupled between the digital phase locked loop and the transmit data path and configured to rotate a phase of a transmit signal based on the smoothened phase error samples.

15. The transmitter circuitry of claim 14 , further comprising:

a signal combiner configured to combine the transmit signal with the carrier signal to generate an RF transmit signal.

16. Receiver circuitry, comprising:

a digital phase locked loop configured to generate a carrier signal and to determine a phase error between a reference signal and the carrier signal;

a digital non-causal linear filter coupled between the digital phase locked loop and a receive data path and configured to generate smoothened phase error samples of the phase error; and

a phase rotator coupled between the digital phase locked loop and the receive data path and configured to rotate a phase of a receive signal based on the smoothened phase error samples.

17. The receiver circuitry of claim 16 , further comprising:

a signal combiner configured to combine a received RF signal with the carrier signal to generate the receive signal.

18. The receiver circuitry of claim 16 , wherein the digital non-causal linear filter is adaptive based on decision feedback of detected data samples.

19. Method for compensating phase fluctuations, comprising:

determining a phase error between a reference signal and an output signal generated by a digital phase locked loop and generating phase error samples;

filtering the phase error samples of the digital phase locked loop with a digital low pass filter; and

rotating a phase of a data signal based on the filtered phase error samples before or after combining the data signal with the output signal.

20. The method of claim 19 , wherein filtering comprises filtering the phase error samples with a non-causal filter.

21. The method of claim 19 , wherein rotating the phase of the data signal comprises rotating the phase of a quadrature modulated signal and/or a polar modulated signal.

Assignments (3)
CONFIRMATORY ASSIGNMENT Recorded Aug 11, 2020
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 053455/0489 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 053065/0418 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2018
From: PERLMUTTER, URI; KERNER, MICHAEL; PARKER, URI
To: INTEL IP CORPORATION
Reel/Frame 046592/0569 →
Cited By (1)
US 12,546,821