IP Library Granted Patent US 10,789,253
Granted Patent B2
US 10,789,253 · App. 16/081,023 · Granted Sep 29, 2020

Computing system and server

Inventors: Kazuhisa Fujimoto (Tokyo, JP); Shinji Fujiwara (Tokyo, JP); Satoru Watanabe (Tokyo, JP); Akira Yamamoto (Tokyo, JP)
Assignee: Hitachi, Ltd.
G06F16/24569G06F3/0604G06F3/064G06F3/067G06F3/0659G06F9/3877
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Quick Facts
Patent No.
US 10,789,253
App. No.
16/081,023
Granted
Sep 29, 2020
Kind
B2
Abstract

A storage device, connected to a computer including a processor and first memory, and executing a program, stores data processed under the program. The computer includes a protocol processing unit that accesses data in the storage device, an accelerator that includes an arithmetic unit executing a part of a process of the program, and a second memory storing data, and executes the part of the process. The first memory receives a processing request for processing data, and causes the accelerator to execute a command to process data, corresponding to the processing request for the processing request including a process to be executed by the arithmetic unit. The accelerator requests the protocol processing unit to provide target data indicated by a command received from the program, reads data from the storage device via the protocol processing unit, and stores the data in the second memory. The arithmetic unit executes the command.

Claims (54)

1. A computing system comprising:

a computer that includes a processor and a first memory, and executes a data processing program; and

a storage device that is connected to the computer via a network, and stores data processed under the data processing program, wherein:

the computer includes

a protocol processing unit that is connected to the network, and accesses data stored in the storage device, and

an accelerator that includes an arithmetic unit connected to the processor and executing a part of a process of the data processing program, and a second memory storing data, and executes the part of the process of the data processing program;

the first memory stores a data processing program that receives a processing request for processing the data, and causes the accelerator to execute a data processing command corresponding to the processing request in a case where the processing request includes a process to be executed by the arithmetic unit, or issues, to the protocol processing unit, a data processing command corresponding to the processing request in a case where the processing request does not include a process to be executed by the arithmetic unit; and

the accelerator requests the protocol processing unit to provide target data indicated by a data processing command received from the data processing program, reads the data from the storage device via the protocol processing unit, and stores the data in the second memory, and subsequently the arithmetic unit that executes the part of the process of the data processing program executes the data processing command,

wherein the protocol processing unit includes a first queue that receives a command from the processor, and a second queue that receives a data processing command from the accelerator, in such a condition that the first queue and the second queue are independent from each other, and

wherein:

the accelerator converts a data processing command received from the data processing program based on a first protocol into a command of a second protocol, and transmits the converted data processing command to the protocol processing unit; and

the protocol processing unit reads, from the storage device, target data indicated by the converted data processing command of the second protocol, and responds to the accelerator.

2. The computing system according to claim 1 , wherein:

the data processing program is a database management program;

the data stored in the storage device is a database; and

the part of the process executed by the arithmetic unit is a searching process.

3. The computing system according to claim 1 , wherein

the first protocol stores a data processing command in the first memory, and causes an issue destination of the data processing command to read the data processing command stored in the first memory.

4. The computing system according to claim 3 , wherein

the first protocol is non-volatile memory express (NVMe) protocol.

5. The computing system according to claim 1 , wherein

the second protocol is a protocol for communicating with the storage device.

6. The computing system according to claim 5 , wherein

the second protocol is a protocol for accessing the storage device in units of block.

7. The computing system according to claim 5 , wherein

the second protocol is a protocol for accessing the storage device in units of file.

8. The computing system according to claim 1 , wherein

the accelerator executes a process designated by the data processing command for the target data read by the protocol processing unit, and transfers a result of the process to the first memory.

9. The computing system according to claim 1 , wherein

the protocol processing unit includes a conversion unit that converts a data processing command received from the data processing program based on a first protocol into a command of the second protocol.

10. The computing system according to claim 9 , wherein

the storage device includes a conversion unit that converts the first protocol into the second protocol, and converts the second protocol into the first protocol.

11. A server that includes a processor and a first memory, and executes a data processing program, wherein:

the server includes

a protocol processing unit that accesses data, and

an accelerator that includes an arithmetic unit connected to the processor and executing a part of a process of the data processing program, and a second memory storing data, and executes the part of the process of the data processing program;

the first memory stores a data processing program that receives a processing request for processing the data, and causes the accelerator to execute a data processing command corresponding to the processing request in a case where the processing request includes a process to be executed by the arithmetic unit, or issues, to the protocol processing unit, a data processing command corresponding to the processing request in a case where the processing request does not include a process to be executed by the arithmetic unit; and

the accelerator requests the protocol processing unit to provide target data indicated by a data processing command received from the data processing program, reads the data via the protocol processing unit, and stores the data in the second memory, and subsequently the arithmetic unit that executes the part of the process of the data processing program executes the data processing command;

wherein the protocol processing unit includes a first queue that receives a command from the processor, and a second queue that receives a data processing command from the accelerator, in such a condition that the first queue and the second queue are independent from each other, and

wherein:

the accelerator converts a data processing command received from the data processing program based on a first protocol into a command of a second protocol, and transmits the converted data processing command to the protocol processing unit; and

the protocol processing unit reads, from the storage device, target data indicated by the converted data processing command of the second protocol, and responds to the accelerator.

12. The server according to claim 11 , wherein:

the data processing program is a database management program;

the data is a database; and

the part of the process executed by the arithmetic unit is a searching process.

13. The server according to claim 11 , wherein

the first protocol stores a data processing command in the first memory, and causes an issue destination of the data processing command to read the data processing command stored in the first memory.

14. The server according to claim 11 , wherein

the first protocol is non-volatile memory express (NVMe) protocol.

15. The server according to claim 11 , wherein

the second protocol is a protocol for communication between the protocol processing unit and an outside.

16. The server according to claim 11 , wherein

the accelerator executes a process designated by the data processing command for the target data read by the protocol processing unit, and transfers a result of the process to the first memory.

Assignments (2)
COMPANY SPLIT Recorded Aug 20, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069518/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2018
From: FUJIMOTO, KAZUHISA; FUJIWARA, SHINJI; WATANABE, SATORU; YAMAMOTO, AKIRA
To: HITACHI, LTD.
Reel/Frame 046747/0957 →
Continuity (1)
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