IP Library Granted Patent US 10,664,193
Granted Patent B2
US 10,664,193 · App. 16/084,916 · Granted May 26, 2020

Storage system for improved efficiency of parity generation and minimized processor load

Inventors: Kenta Shinozuka (Tokyo, JP); Takahiko Takeda (Tokyo, JP); Isamu Kurokawa (Tokyo, JP); Sho Sawada (Tokyo, JP)
Assignee: HITACHI, LTD.
G06F3/0658G06F3/061G06F3/064G06F3/0619G06F3/0659G06F3/0673G06F3/0688G06F11/108G06F11/1096
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Quick Facts
Patent No.
US 10,664,193
App. No.
16/084,916
Granted
May 26, 2020
Kind
B2
Abstract

A controller is configured to receive a write request from a host, and send an intermediate parity generation command corresponding to a specified address indicated by the write request to a first storage device in storage devices. The intermediate parity generation command instructs generation of an intermediate parity from new data at the specified address and old data that is updated to the new data. The intermediate parity generation command includes a first address in the memory area at which the new data is stored and a second address in the memory area for storing the intermediate parity. The first storage device is configured to receive the intermediate parity generation command, acquire the new data from the first address, generate the intermediate parity from the new data and the old data stored in the first storage device, and store the intermediate parity at the second address.

Claims (49)

1. A storage system, comprising:

a controller with a memory area; and

a plurality of storage devices each including a storage medium, the controller being configured to:

receive a write request from a host; and

send an intermediate parity generation command corresponding to a specified address indicated by the write request to a first storage device in the plurality of storage devices,

wherein the intermediate parity generation command instructs generation of an intermediate parity from new data at the specified address and old data that is updated to the new data,

wherein the intermediate parity generation command includes a first address in the memory area at which the new data is stored and a second address in the memory area for storing the intermediate parity,

wherein the first storage device is configured to receive the intermediate parity generation command, acquire the new data from the first address, generate the intermediate parity from the new data and the old data stored in the first storage device, and store the intermediate parity at the second address, and

wherein the controller includes a plurality of processors;

a first processor in the plurality of processors is configured to start processing the write request and store write request management information indicating a processing phase of the write request in a shared storage area using the plurality of processors; and

a second processor in the plurality of processors is configured to take over processing of the write request in response to an error in the first processor and refer to the write request management information in the shared storage area to identify a phase of processing of the write request.

2. The storage system according to claim 1 , wherein:

the controller sends a new parity generation command to a second storage device in the plurality of storage devices;

the new parity generation command instructs generation of a new parity from the intermediate parity and an old parity related to old data at the specified address;

the new parity generation command includes the second address; and

the second storage device is configured to receive the new parity generation command, read out the intermediate parity from the second address, and generate the new parity from the intermediate parity and the old parity stored in the second storage device.

3. The storage system according to claim 1 , wherein, in a case where the write request management information indicates pre-generation of the new parity, the second processor sends, to each of the first storage device and the second storage device, a reset command instructing the first storage device and the second storage device to stop processing the intermediate parity generation command and the new parity generation command.

4. The storage system according to claim 3 , wherein the first storage device is configured to:

manage the specified address, mapping information indicating a correlation between the specified address and an address of a storage medium in the first storage device at which data on the specified address is stored, and an address of the storage medium in the first storage device at which the old data is stored;

store the new data at an address in the storage medium of the first storage device different to that of the old data;

update an address corresponding to the specified address to an address of the new data in the mapping information; and

writeback the address corresponding to the specified address with an address of the old data in the mapping information in response to the reset command.

5. The storage system according to claim 1 , wherein:

the first storage device stores the new data at an address different to that of the old data in the storage medium of the first storage device;

the second storage device stores the new parity at an address different to that of the old parity in the storage medium of the second storage device; and

in a case where the write request management information indicates pre-generation of the new parity, the second processor acquires data in stripe columns that contain the new data from the plurality of storage devices to generate a parity from the acquired data in the stripe columns and store the parity in the second storage device.

6. A method of storing data in a storage system including a controller with a memory area and a plurality of storage devices each including a storage medium, wherein:

the controller receives a write request from a host, wherein the controller includes a plurality of processors;

a first processor in the plurality of processors is configured to start processing the write request and store write request management information indicating a processing phase of the write request in a shared storage area using the plurality of processors;

a second processor in the plurality of processors is configured to take over processing of the write request in response to an error in the first processor and refer to the write request management information in the shared storage area to identify a phase of processing of the write request;

the controller sends an intermediate parity generation command corresponding to a specified address indicated by the write request to a first storage device in the plurality of storage devices;

the intermediate parity generation command instructs generation of an intermediate parity from new data of the specified address and old data that is updated to the new data;

the intermediate parity generation command includes a first address of the memory area that stores the new data and a second address of the memory area for storing the intermediate parity; and

the first storage device receives the intermediate parity generation command, acquires the new data from the first address, generates the intermediate parity from the new data and the old data stored in the first storage device, and stores the intermediate parity at the second address.

7. The method according to claim 6 , wherein:

the controller sends a new parity generation command to a second storage device in the plurality of storage devices;

the new parity generation command instructs generation of a new parity from the intermediate parity and an old parity related to old data at the specified address;

the new parity generation command includes a second address; and

the second storage device receives the new parity generation command, reads out the intermediate parity from the second address, and generates the new parity from the intermediate parity and the old parity stored in the second storage device.

8. The method according to claim 6 , wherein, in a case where the write request management information indicates pre-generation of the new parity, the controller sends, to each of the first storage device and the second storage device, a reset command instructing the first storage device and the second storage device to stop processing the intermediate parity generation command and the new parity generation command.

9. The method according to claim 8 , wherein the first storage device is configured to:

manage the specified address, mapping information indicating a correlation between the specified address and an address of a storage medium in the first storage device at which data on the specified address is stored, and an address of the storage medium in the first storage device at which the old data is stored;

store the new data at an address in the storage medium of the first storage device that is different to that of the old data;

update an address corresponding to the specified address to an address of the new data in the mapping information; and

writeback the address corresponding to the specified address with address of the old data in the mapping information in response to the reset command.

10. The method according to claim 6 , wherein:

the first storage device stores the new data at an address different to that of the old data in the storage medium of the first storage device;

the second storage device stores the new parity at an address different to that of the old parity in the storage medium of the second storage device; and

in a case where the write request management information indicates pre-generation of the new parity, the second processor acquires data in stripe columns that contain the new data from the plurality of storage devices to generate a parity from the acquired data in stripe columns and store the parity in the second storage device.

Assignments (3)
COMPANY SPLIT Recorded Aug 20, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069518/0761 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SPEELLING OF ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 046871 FRAME: 0979. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 21, 2018
From: SHINOZUKA, KENTA; TAKEDA, TAKAHIKO; KUROKAWA, ISAMU; SAWADA, SHO
To: HITACHI, LTD.
Reel/Frame 047585/0945 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2018
From: SHINOZUKA, KENTA; TAKEDA, TAKAHIKO; KUROKAWA, ISAMU; SAWADA, SHO
To: HITACHI, LTD,
Reel/Frame 046871/0979 →
Continuity (1)
Related Publication 20190087122A1 · Mar 21, 2019
Cited By (1)
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