Systems and methods for superconducting devices used in superconducting circuits and scalable computing
Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
1. A system, comprising:
a first set of digital-to-analog converters (DACs), each of the DACs of the first set of DACs including a respective loop of material and a respective pair of Josephson junctions that interrupt the respective loop of material and are electrically coupled in parallel with one another in the respective loop of material;
a first quantum flux parametron (QFP) based shift register comprising a sequence of a plurality of QFP-based shift register elements, the first QFP-based shift register one of magnetically or galvanically coupleable to the DACs of the first set of DACs;
a power line that serially couples the DACs of the first set of DACs; and
a trigger line that serially couples the DACs of the first set of DACs, wherein:
each of the DACs of the first set of DACs is independently addressable by a triplet of three signals a successive number of times to store a variable number of flux quanta, the triplet of three signals including a first signal received via the QFP-based shift register elements of the first QFP-based shift register, a second signal received via the power line, and a third signal received via the trigger line.
2. The system of claim 1 , further comprising:
an inductor ladder circuit that superconducts at a critical temperature and that includes a plurality of inductors, wherein each of the QFP-based shift register element of the first QFP-based shift register is magnetically coupled to one of the DACs of the first set of DACs via the inductor ladder circuit.
3. The system of claim 1 , further comprising:
a first set of QFP amplifiers that galvanically couple to respective ones of the DACs of the first set of DAC as a respective flux amplifier.
4. The system of claim 3 wherein each of the QFP amplifiers of the first set of QFP amplifiers includes a respective loop of material that superconducts at a critical temperature and a respective pair of Josephson junctions that interrupt the respective loop and are electrically coupled in parallel with one another in the loop of material.
5. The system of claim 3 , and further comprising:
an inductor ladder circuit that superconducts at a critical temperature and that includes a plurality of inductors, wherein each of the QFP amplifiers of the first set of QFP amplifiers is coupled between a respective one of the DACs of the first set of DACs and the QFP-based shift register elements of the first QFP-based shift register via the inductor ladder circuit.
6. The system of claim 1 wherein the first QFP-based shift register includes at least three QFP register elements per DAC of the first set of DACs.
7. The system of claim 6 wherein each of the QFP register elements of the first QFP-based shift register includes a respective loop of material that superconducts at a critical temperature and a respective pair of Josephson junctions that interrupt the respective loop and are electrically coupled in parallel with one another in the loop of material.
8. The system of claim 7 wherein each of the QFP register elements of the first QFP-based shift register includes a respective galvanic interface to one of a plurality of address lines.
9. The system of claim 7 , further comprising:
a plurality of additional sets of DACs; and
a plurality of additional QFP-based shift registers.
10. The system of claim 6 , further comprising:
control circuitry communicatively coupled to apply signals to the power line, the trigger line and an address line.
11. The system of claim 10 wherein the control circuitry sequentially applies signals to the power line, the trigger line and the address line to load single flux quanta (SFQ) to selected ones of the DACs.
12. The system of claim 10 wherein the control circuitry:
resets all of the DACs of the first set of DACs;
applies a clockwise persistent current to a first number of the QFP-based shift register elements which are coupled to the DACs into which quantums of flux are to be added;
applies a counter-clockwise persistent current to a second number of the QFP-based shift register elements which are coupled to the DACs into which quantums of flux are not to be loaded; and
for a first number of times, applies a signal to the trigger line, where the first number of times is at least proportional to a total number of quantums of flux to be added.
13. The system of claim 12 wherein the first number of times is equal to the total number of quantums of flux to be loaded.
14. The system of claim 10 wherein the control circuitry:
sorts all of the DACs based on a number of quantums of flux to be loaded to the DACs;
resets all of the DACs;
applies a clockwise persistent current to a number of the QFP-based shift register elements which are coupled to the DAC stages into which at least one quantum of flux is to be loaded;
applies a counter-clockwise persistent current to a number of the QFP-based shift register elements which are coupled to the DACs into which less than one quantum of flux is to be loaded;
applies a signal to the trigger line;
applies a clockwise persistent current to a number of the QFP-based shift register elements which are coupled to the DACs into which at least two quantums of flux are to be loaded;
applies a counter-clockwise persistent current to a number of the QFP-based shift register elements which are coupled to the DACs into which less than two quantums of flux are to be loaded; and
applies a signal to the trigger line.
15. The system of claim 10 wherein the control circuitry:
sorts all of the DAC stages based on a number of quantums of flux to be loaded to the DACs;
resets all of the DACs of all of the DAC stages; and
for an integer number i times from i equals 1 to a maximum number of quantums of flux n to be programmed:
applies a clockwise persistent current to a number of the QFP-based shift register elements which are coupled to the DACs into which at least i quantums of flux are to be loaded;
applies a counter-clockwise persistent current to a number of the QFP-based shift register elements which are coupled to the DACs into which less than i quantums of flux are to be loaded; and
applies a signal to the trigger line.
16. The system of claim 15 wherein the maximum number of quantums of flux n is between 18 and 22.
17. The system of claim 10 wherein to reset all of the DACs of the first set of DACs, the control circuitry repeatedly applies a signal to the trigger line.
18. The system of claim 1 , further comprising:
a second set of DACs, each of the DACs of the second set of DACs including a respective loop of material that superconducts at a critical temperature and a respective pair of Josephson junctions that interrupt the respective loop and are electrically coupled in parallel with one another in the loop of material;
a second QFP-based shift register comprising a sequence of a plurality of QFP-based shift register elements, the QFP-based shift register elements of the second QFP-based shift register one of magnetically or galvanically coupleable to the DACs of the second set of DACs; and
each of the DACs of the second set of DACs is independently addressable by a triplet of three signals a successive number of times to store a variable number of flux quanta, the triplet of three signals including a first received via the QFP-based shift register elements of the second QFP-based shift register, a second signal, and signal a third signal.
19. The system of claim 1 wherein the respective loop of material of each of the DACs superconducts at least at a critical temperature and all of the DACS and QFP-based shift register reside on a single chip.
20. A system, comprising:
a number of quantum flux parametrons (QFPs);
at least one pair of quantum flux parametron digital-to-analog converters (QFP-DACs);
a current bias line that applies a current bias to both of the QFP-DACs of the at least one pair of the QFP-DACs without any bias resistors; and
for each QFP of the number of QFPs, a respective first number of quantum flux parametron-latches (QFP-latches) selectively operable to communicatively couple flux between the QFP and a first one of the QFP-DACs of the at least one pair of QFP-DACs and a respective second number of QFP-latches selectively operable to communicatively couple flux between the QFP and a second one of the QFP-DACs of the at least one pair of QFP-DACs.
21. The system of claim 20 wherein each of the QFPs includes a respective first loop of material interrupted by a respective second loop of material, the first and the second loops of material which are superconductive at a critical temperature, and having a respective first and a respective second interface, the second loop of material interrupted by two Josephson junctions, the first inductive interface positioned to communicatively couple flux with the first one of the respective first number of QFP-latches and the second inductive interface positioned to communicatively couple flux with the first one of the respective second number of QFP-latches.
22. The system of claim 20 wherein each of the QFPs includes a respective loop with a first interface positioned to communicatively couple flux to a first one of the respective first number of QFP-latches and a second interface positioned to communicatively couple flux to a first one of the respective second number of QFP-latches.
23. The system of claim 20 wherein each of the first one of the respective first number of QFP-latches includes a respective loop with a respective second interface positioned to communicatively couple flux to a second one of the respective first number of QFP-latches, and each of the first one of the respective second number of QFP-latches includes a respective loop with a respective second interface positioned to communicatively couple flux to a second one of the respective second number of QFP-latches.
24. The system of claim 23 wherein the first one of each of the first number of QFP-latches is responsive to a respective first latch signal and the first one of each of the second number of QFP-latches is responsive to a logical inverse of the respective first latch signal.
25. The system of claim 20 , further comprising:
control circuitry communicatively coupled to apply signals to the QFP-DACs and the QFP-latches.
26. The system of claim 25 wherein the control circuitry applies signals to the QFP-latches to load information into the DACs and/or from the DACs.
27. The system of claim 20 wherein all of the QFPs QFP-DACs and QFP-latches form a non-dissipative programmable magnetic memory (PMM) that resides on a single chip.