Semiconductor constructions, methods of forming vertical memory strings, and methods of forming vertically-stacked structures

1. A memory device, comprising:

a stack of alternating electrically conductive levels and electrically insulative levels over a material comprising tungsten silicide;

electrically insulative pillars that extends through the stack and contact

an upper surface of the material comprising tungsten silicide;

a channel material post between a first adjacent pair of the pillars, the channel material post extending through the material comprising tungsten silicide and having a first pair of opposing sides and a second pair of opposing sides; each side of the first pair of opposing sides being spaced from a respective one of a second adjacent pair of the pillars by a corresponding intervening region of the stack; none of the stack being present between each side of the second pair of opposing sides and a respective one of the first adjacent pair of the pillars;

gate dielectric material and charge-storage material between edges of the electrically conductive levels and the channel material post.

2. The memory device of claim 1 , further comprising charge blocking material between edges of the electrically conductive levels and the channel material post.

3. The memory device of claim 2 , wherein at least some of the electrically conductive levels of the stack comprise control gates.

4. The memory device of claim 3 , wherein the charge blocking material is disposed between and contacts the control gates and the charge-storage material.

5. The memory device of claim 4 , wherein the charge storage material is in contact with the gate dielectric material.

6. The memory device of claim 5 , wherein each of the charge storage material, the charge blocking material and the control gates are in contact with electrically insulative material of the electrically insulative levels.

7. The memory device of claim 5 , wherein the charge blocking material comprises a plurality of charge blocking materials.

8. The memory device of claim 7 , wherein the plurality of charge blocking materials comprise a first charge blocking material comprising an oxide material, a second charge blocking material comprising a nitride material and a third charge blocking material comprising an oxide material.

9. A memory device, comprising:

an etchstop material over a semiconductor base;

a stack of alternating electrically conductive levels comprising control gates and electrically insulative levels over the etchstop material;

electrically insulative pillars extending through the stack and contacting an upper surface of the etchstop material;

a channel material post between a first adjacent pair of the pillars; the channel material post extending through the etchstop material and having a first pair of opposing sides and a second pair of opposing sides; each side of the first pair of opposing sides being spaced from a respective one of a second adjacent pair of the pillars by a corresponding intervening region of the stack; none of the stack being present between each side of the second pair of opposing sides and a respective one of the first adjacent pair of the pillars;

charge-storage material;

charge blocking material disposed between and contacting the control gates and the charge-storage material; and

gate dielectric material between the charge-storage material and the channel material post.

10. The memory device of claim 9 , wherein the charge-storage material comprises polycrystalline silicon.

11. The memory device of claim 9 , wherein the charge-storage material comprises silicon nitride.

12. The memory device of claim 9 , wherein the post and pillars are part of a serpentining structure that extends through the stack.