Providing recovered data to a new memory cell at a memory sub-system based on an unsuccessful error correction operation
At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.
1. A system comprising:
a memory component; and
a processing device, operatively coupled with the memory component, to:
adjust a program verify voltage associated with a set of data stored at a first memory cell of the memory component to cause a first error rate of at least one data of the set of data to exceed a second error rate of the set of data;
determine that the at least one data of the set of data stored at the first memory cell of the memory component is associated with an unsuccessful error correction operation;
determine that a programming operation associated with the set of data stored at the first memory cell has completed;
in response to determining that the programming operation associated with the set of data stored at the first memory cell has completed, recover the at least one data of the set of data stored at the first memory cell that is associated with the unsuccessful error correction operation;
in response to recovering the at least one data of the set of data stored at the first memory cell that is associated with the unsuccessful error correction operation, identify a second memory cell of the memory component; and
provide the set of data comprising the recovered at least one data to the second memory cell of the memory component.
2. The system of claim 1 , wherein the processing device is further to:
receive second data associated with the at least one data of the set of data stored at the first memory cell; and
provide the second data associated with the at least one data of the set of data to the second memory cell of the memory component based on the recovered at least one data.
3. The system of claim 1 , wherein the second memory cell is located on a different block of the memory component as the first memory cell.
4. The system of claim 1 , wherein determining that the at least one data of the set of data stored at the first memory cell of the memory component is associated with the unsuccessful error correction operation is in response to performing a read operation on the at least one data of the set of data stored at the first memory cell of the memory component.
5. The system of claim 4 , wherein the read operation is performed on the at least one data of the set of data stored at the first memory cell of the memory component before a second programming pass of a two-pass programming operation.
6. The system of claim 1 , wherein recovering the at least one data of the set of data stored at the first memory cell that is associated with the unsuccessful error correction operation is based on parity data associated with the data.
7. The system of claim 1 , wherein to determine that the at least one data of the set of data stored at the first memory cell of the memory component is associated with the unsuccessful error correction operation, the processing device is further to:
determine that identification information associated with the at least one data of the set of data is stored in a data structure indicating the at least one data of the set of data stored at the first memory cell of the memory component is associated with the unsuccessful error correction operation.
8. A method comprising:
performing a plurality of programming operations to provide one or more pages of data to a first memory cell of a memory component;
determining that at least one page of the one or more pages of data provided to the first memory cell during the plurality of programming operations is associated with an unsuccessful error correction operation, wherein the determining includes adjusting a program verify voltage associated with the one or more pages to cause a first error rate of the at least one page to exceed a second error rate of a set of data; and
in response to determining that the at least one page is associated with the unsuccessful error correction operation, performing, by a processing device, a recovery operation on the at least one page.
9. The method of claim 8 , further comprising:
providing the recovered at least one of the one or more pages of data to a second memory cell of the memory component.
10. The method of claim 9 , wherein the second memory cell is located on a different block of the memory component as the first memory cell.
11. The method of claim 8 , further comprising:
performing a subsequent read or write operation on the memory component, wherein determining that the at least one of the one or more pages of data provided to the first memory cell during the plurality of programming operations is based on completion of the performance of the subsequent read or write operation on the memory component.
12. The method of claim 8 , further comprising:
performing a folding operation on the first memory cell of the memory component based on the at least one of the one or more pages of data provided to the first memory cell is associated with the unsuccessful error correction operation.
13. The method of claim 8 , wherein the recovery operation on the at least one of the one or more pages of data based on parity data associated with the set of data.
14. The method of claim 8 , wherein determining that the at least one of the one or more pages of data provided to the first memory cell during the plurality of programming operations is associated with the unsuccessful error correction operation comprises:
determining that identification information associated with the at least one of the one or more pages of data is stored in a data structure indicating the at least one of the one or more pages of data provided to the first memory cell of the memory component is associated with the unsuccessful error correction operation.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
adjust a program verify voltage associated with a set of data stored at a first memory cell of a memory component to cause a first error rate of at least one data of the set of data to exceed a second error rate of the set of data;
determine that the first error rate is associated with an unsuccessful error correction operation;
determine that a programming operation associated with the set of data stored at the first memory cell has completed;
in response to determining that the programming operation associated with the set of data stored at the first memory cell has completed, recover the at least one data of the set of data stored at the first memory cell that is associated with the unsuccessful error correction operation;
in response to recovering the at least one data of the set of data stored at the first memory cell that is associated with the unsuccessful error correction operation, identify a second memory cell of the memory component; and
provide the set of data comprising the recovered at least one data to the second memory cell of the memory component.
16. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is further to:
receive second data associated with the at least one data of the set of data stored at the first memory cell; and
provide the second data associated with the at least one data of the set of data to the second memory cell of the memory component based on the recovered at least one data.
17. The non-transitory computer-readable storage medium of claim 15 , wherein the second memory cell is located on a different block of the memory component as the first memory cell.
18. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is further to:
perform a read operation on the at least one data of the set of data stored at the first memory cell of the memory component, wherein determining that the at least one data of the set of data stored at the first memory cell of the memory component is associated with the unsuccessful error correction operation is in response to performing the read operation on the at least one data of the set of data stored at the first memory cell of the memory component.
19. The non-transitory computer-readable storage medium of claim 15 , wherein recovering the at least one data of the set of data stored at the first memory cell that is associated with the unsuccessful error correction operation is based on parity data associated with the data.
20. The non-transitory computer-readable storage medium of claim 15 , wherein to determine that the at least one data of the set of data stored at the first memory cell of the memory component is associated with the unsuccessful error correction operation, the processing device is further to:
determine that identification information associated with the at least one data of the set of data is stored in a data structure indicating the at least one data of the set of data stored at the first memory cell of the memory component is associated with the unsuccessful error correction operation.