Bank to bank data transfer
The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.
1. An apparatus, comprising:
a bank-to-bank transfer (BBT) bus coupled to a plurality of banks of memory cells; and
a controller coupled to the BBT bus and configured to:
determine a shortest transfer time for transfer of data between the plurality of banks; and
control transfer of data between the plurality of banks based on the determination.
2. The apparatus of claim 1 , wherein the controller is further configured to determine the shortest transfer time and control transfer of the data without transferring the data to circuitry external to the plurality of banks.
3. The apparatus of claim 1 , wherein the controller is further configured to determine the shortest transfer time and control transfer of the data without transferring the data via an external bus interface coupled to the plurality of banks.
4. The apparatus of claim 1 , wherein the BBT bus comprises a token ring architecture.
5. The apparatus of claim 1 , wherein the controller is further configured to control transfer of the data by controlling transfer of first data in a first direction around the BBT bus and controlling transfer of second data in a second direction around the BBT bus.
6. The apparatus of claim 5 , wherein the controller is further configured to control transfer in the first direction concurrently with transfer in the second direction.
7. The apparatus of claim 1 , wherein the controller is further configured to reconfigure the BBT bus based, at least in part, on the determination.
8. The apparatus of claim 7 , wherein the controller is further configured to cause data on the BBT bus to be cleared from the BBT bus in response to reconfiguration of the BBT bus.
9. A system, comprising:
a host;
a memory device coupled to the host and comprising a bank-to-bank transfer (BBT) bus coupled to each of a plurality of memory banks, wherein the memory device is configured to:
receive a command from the host to initiate a data transfer operation;
cause a transfer of first data between the plurality of memory banks in a first direction in response to a determination that transfer of first data in the first direction yields a shortest transfer time of data between the plurality of memory banks; and
transfer second data between the plurality of memory banks in a second direction in response to a determination that transfer of second data in the second direction yields a shortest transfer time of data between the plurality of memory banks.
10. The system of claim 9 , wherein the first direction and the second direction are opposite directions.
11. The system of claim 9 , wherein the BBT bus is to control transfer of the first data and the second data without transferring data from the memory device to the host.
12. The system of claim 9 , further comprising an external bus configured to transfer data from the plurality of banks to a memory array coupled to the banks concurrently with transfer of the first data and the second data via the BBT bus.
13. The system of claim 9 , wherein the BBT bus is further configured to transfer the first data in the first direction concurrently with transfer of the second data in the second direction.
14. The system of claim 9 , wherein the BBT bus is configured to transfer the first data, the second data, or combinations thereof, according to a first in first out policy.
15. The system of claim 9 , wherein the memory device further comprises a controller coupled to the BBT bus and configured to cause the BBT bus to be reconfigured to optimize transfer of the first data, the second data, or combinations thereof.
16. A method, comprising:
determining, by a controller coupled to a bank-to-bank transfer (BBT) bus, a shortest transfer time for transfer of data between a plurality of memory banks that are coupled to the BBT bus; and
controlling, by the controller, transfer of data between the plurality of memory banks based on the determination.
17. The method of claim 16 , further comprising:
determining, by the controller, the shortest transfer time without transferring the data to circuitry external to the plurality of memory banks; and
controlling, by the controller, the transfer of data between the plurality of memory banks time without transferring the data to circuitry external to the plurality of memory banks.
18. The method of claim 16 , further comprising:
reconfiguring, by the controller, the BBT bus based, at least in part on the determination; and
causing, by the controller, data on the BBT bus to be cleared from the BBT bus in response to reconfiguration of the BBT bus.
19. The method of claim 16 , further comprising controlling, by the controller, transfer of first data in a first direction around the BBT bus and controlling transfer of second data in a second direction around the BBT bus.
20. The method of claim 16 , further comprising controlling, by the controller, transfer of the first data in the first direction concurrently with transfer of the second data in the second direction.