Disturb-optimized codeword layout

1. A method comprising:

writing a first bit of an aggressor codeword to a first memory cell, wherein the write to the first memory cell disturbs a set of one or more victim codewords by contributing to a cumulative effect that can change a value of a victim codeword in the set based on proximity to the first memory cell;

writing a second bit of the aggressor codeword to a second memory cell, wherein the write to the second memory cell disturbs at most the one or more victim codewords of the set by contributing to the cumulative effect based on proximity to the second memory cell; and

wherein the second memory cell is separated from the first memory cell by at least a third memory cell, wherein the third memory cell stores a first bit of a second codeword.

2. The method of claim 1 , wherein the second memory cell is further separated from the first memory cell by at least a fourth memory cell, wherein the fourth memory cell does not store data of a codeword.

3. The method of claim 1 , wherein a total number of memory cells separating the first memory cell and the second memory cell is based on a size of the aggressor codeword.

4. The method of claim 1 , further comprising:

writing a first portion of the aggressor codeword across each of N partitions of a memory die, where N is a number of partitions on the memory die and is greater than one, and wherein the first portion of the aggressor codeword includes the first bit; and

writing a second portion of the aggressor codeword across each of M partitions of the memory die, where M is greater than or equal to one and less than N, and wherein the second portion of the aggressor codeword includes the second bit.

5. The method of claim 1 , further comprising:

writing a third bit of the aggressor codeword to a fourth memory cell;

writing a fourth bit of the aggressor codeword to a fifth memory cell, wherein the fifth memory cell is separated from the fourth memory cell by at least a sixth memory cell, wherein the sixth memory cell stores a second bit of the second codeword; and

wherein the first memory cell, the second memory cell, and the third memory cell are on a first partition of a memory die and the fourth memory cell, the fifth memory cell, and the sixth memory cell are on a second partition of the memory die.

6. The method of claim 1 , wherein the first memory cell and the second memory cell are at different page locations within different partitions of a memory die.

7. The method of claim 1 , wherein the set includes a first victim codeword that includes data that is stored in a first victim memory cell offset in a first dimension from the first memory cell and data that is stored in a second memory cell offset in the first dimension from the second memory cell.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

write a first bit of an aggressor codeword to a first memory cell, wherein the write to the first memory cell disturbs a set of one or more victim codewords by contributing to a cumulative effect that can change a value of a victim codeword in the set based on proximity to the first memory cell;

write a second bit of the aggressor codeword to a second memory cell, wherein the write to the second memory cell disturbs at most the one or more victim codewords of the set by contributing to the cumulative effect based on proximity to the second memory cell; and

wherein the second memory cell is separated from the first memory cell by at least a third memory cell, wherein the third memory cell stores a first bit of a second codeword.

9. The non-transitory computer-readable storage medium of claim 8 , wherein the second memory cell is further separated from the first memory cell by at least a fourth memory cell, wherein the fourth memory cell does not store data of a codeword.

10. The non-transitory computer-readable storage medium of claim 8 , wherein a total number of memory cells separating the first memory cell and the second memory cell is based on a size of the aggressor codeword.

11. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

write a first portion of the aggressor codeword across each of N partitions of a memory die, where N is a number of partitions on the memory die and is greater than one, and wherein the first portion of the aggressor codeword includes the first bit; and

write a second portion of the aggressor codeword across each of M partitions of the memory die, where M is greater than or equal to one and less than N, and wherein the second portion of the aggressor codeword includes the second bit.

12. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

write a third bit of the aggressor codeword to a fourth memory cell;

write a fourth bit of the aggressor codeword to a fifth memory cell, wherein the fifth memory cell is separated from the fourth memory cell by at least a sixth memory cell, wherein the sixth memory cell stores a second bit of the second codeword; and

wherein the first memory cell, the second memory cell, and the third memory cell are on a first partition of a memory die and the fourth memory cell, the fifth memory cell, and the sixth memory cell are on a second partition of the memory die.

13. The non-transitory computer-readable storage medium of claim 8 , wherein the first memory cell and the second memory cell are at different page locations within different partitions of a memory die.

14. The non-transitory computer-readable storage medium of claim 8 , wherein the set includes a first victim codeword that includes data that is stored in a first victim memory cell offset in a first dimension from the first memory cell and data that is stored in a second memory cell offset in the first dimension from the second memory cell.

15. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, configured to:

write a first bit of an aggressor codeword to a first memory cell, wherein the write to the first memory cell disturbs a set of one or more victim codewords by contributing to a cumulative effect that can change a value of a victim codeword in the set based on proximity to the first memory cell;

write a second bit of the aggressor codeword to a second memory cell, wherein the write to the second memory cell disturbs at most the one or more victim codewords of the set by contributing to the cumulative effect based on proximity to the second memory cell; and

write a first bit of a second codeword to a third memory cell; and

wherein the second memory cell is separated from the first memory cell by at least a third memory cell and the set includes a first victim codeword that includes data that is stored in a first victim memory cell offset in a first dimension from the first memory cell and data that is stored in a second memory cell offset in the first dimension from the second memory cell.

16. The system of claim 15 , wherein the second memory cell is further separated from the first memory cell by at least a fourth memory cell, wherein the fourth memory cell does not store data of a codeword.

17. The system of claim 15 , wherein a total number of memory cells separating the first memory cell and the second memory cell is based on a size of the aggressor codeword.

18. The system of claim 15 , wherein the processing device is further to:

write a first portion of the aggressor codeword across each of N partitions of a memory die, where N is a number of partitions on the memory die and is greater than one, and wherein the first portion of the aggressor codeword includes the first bit; and

write a second portion of the aggressor codeword across each of M partitions of the memory die, where M is greater than or equal to one and less than N, and wherein the second portion of the aggressor codeword includes the second bit.

19. The system of claim 15 , wherein the processing device is further to:

write a third bit of the aggressor codeword to a fourth memory cell;

write a fourth bit of the aggressor codeword to a fifth memory cell, wherein the fifth memory cell is separated from the fourth memory cell by at least a sixth memory cell, wherein the sixth memory cell stores a second bit of the second codeword; and

wherein the first memory cell, the second memory cell, and the third memory cell are on a first partition of a memory die and the fourth memory cell, the fifth memory cell, and the sixth memory cell are on a second partition of the memory die.

20. The system of claim 15 , wherein the first memory cell and the second memory cell are at different page locations within different partitions of a memory die.