Pulse-width modulated multiplier
Disclosed herein is a neuromorphic integrated circuit, including in many embodiments, a neural network disposed in a multiplier array in a memory sector of the integrated circuit, and a plurality of multipliers of the multiplier array, a multiplier thereof including at least one transistor-based cell configured to store a synaptic weight of the neural network, an input configured to accept digital input pulses for the multiplier, an output configured to provide digital output pulses of the multiplier, and a charge integrator, where the charge integrator is configured to integrate a current associated with an input pulse of the input pulses over an input pulse width thereof, and where the multiplier is configured to provide an output pulse of the output pulses with an output pulse width proportional to the input pulse width.
1. A neuromorphic integrated circuit, comprising:
a neural network disposed in a multiplier array in a memory sector of the integrated circuit; and
a plurality of multipliers of the multiplier array, a multiplier thereof including at least:
a transistor-based cell comprising at least a positive transistor and a negative transistor, configured to store a synaptic weight of the neural network;
an input configured to accept digital input pulses for the multiplier;
an output configured to provide digital output pulses of the multiplier; and
a charge integrator,
wherein the charge integrator is configured to integrate a current associated with an input pulse of the input pulses over an input pulse width thereof;
wherein the power consumption of either the positive transistor or negative transistor is approximately zero in response to a digital input value of approximately zero; and
wherein the multiplier is configured to provide an output pulse of the output pulses with an output pulse width proportional to the input pulse width.
2. The neuromorphic integrated circuit of claim 1 , wherein inputs for the input pulses of the plurality of multipliers and outputs for the output pulses of the plurality of multipliers provide the neural network with digital routing between layers of the neural network.
3. The integrated circuit of claim 1 , wherein the power consumption of either the positive transistor or negative transistor is approximately zero in response to a synaptic weight value of approximately zero.
4. The integrated circuit of claim 1 , wherein the multiplier is further configured to provide an output pulse in response to an input integrated voltage and an input ramping voltage.
5. The integrated circuit of claim 1 , wherein the multiplier is a two-quadrant multiplier.
6. The integrated circuit of claim 5 , wherein the two-quadrant multiplier comprises a positive voltage input and a negative voltage input that can be utilized for erasure by setting the transistor-based cell to an extreme synaptic weight value by programming of the positive and negative input voltages.
7. The integrated circuit of claim 6 , wherein overshoot can be compensated for in the two-quadrant multiplier by re-programming the positive input voltage with an increased synaptic weight value in response to a synaptic weight value in the negative voltage input greater than the initially programmed synaptic weight value.
8. The integrated circuit of claim 1 , wherein the charge integrator outputs a voltage based on the multiplication of the input pulse width associated with the signal timing, and a current that is associated with the synaptic weight value.
9. The integrated circuit of either claim 1 or 2 , wherein the integrated circuit is configured to operate on battery power.
10. A method, comprising:
integrating with an integrator a current associated with a digital input pulse of a plurality of digital input pulses over an input pulse width of the input pulse; and
providing with a multiplier a digital output pulse of a plurality of digital output pulses having an output pulse width proportional to the input pulse width,
wherein the multiplier is one of a plurality of multipliers of a multiplier array in a memory sector of a neuromorphic integrated circuit, and
wherein the multiplier includes at least:
a transistor-based cell comprising at least one positive transistor and one negative transistor, the transistor-based cell configured to store a synaptic weight of a plurality of synaptic weights of a neural network disposed in the multiplier array;
an input configured to accept the input pulses for the multiplier;
an output configured to provide the output pulses of the multiplier; and
the charge integrator; and
wherein the power consumption of either the positive transistor or negative transistor is approximately zero in response to a digital input current value of approximately zero.
11. The method of claim 10 , further comprising:
digitally routing between layers of the neural network,
wherein inputs for the input pulses of the plurality of multipliers and outputs for the output pulses of the plurality of multipliers provide the neural network with digital routing between the layers of the neural network.
12. The method of claim 11 , wherein the power consumption of either the positive transistor or negative transistor is approximately zero in response to a synaptic weight value of approximately zero.
13. The method of claim 10 , wherein the multiplier is a two-quadrant multiplier.
14. The method of claim 13 , wherein the two-quadrant multiplier comprises a positive voltage input and a negative voltage input that can be utilized for erasure by setting the transistor-based cell to an extreme synaptic weight value by programming of the positive and negative input voltages.