Boosting a digit line voltage for a write operation
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. The magnitude of a voltage applied across a ferroelectric capacitor may be dynamically increased during a write operation. A memory cell may be selected for a write operation, and a voltage may be applied to a digit line corresponding to the memory cell during the write operation. An additional charge may be transferred to the digit line—e.g., from an energy storage component, such as a capacitor, that is in electronic communication with the digit line. In turn, the voltage across the ferroelectric capacitor of the memory cell may be increased.
1. A method, comprising:
applying, during a write operation, a first voltage to a digit line coupled with a memory cell;
coupling a boost component to the digit line during the write operation based at least in part on applying the first voltage; and
boosting the digit line to a second voltage during the write operation based at least in part on coupling the boost component to the digit line.
2. The method of claim 1 , further comprising:
applying a third voltage to a node of the boost component after coupling the boost component with the digit line, wherein boosting the digit line to the second voltage is based at least in part on applying the third voltage to the node of the boost component.
3. The method of claim 1 , further comprising:
determining that a magnitude of a signal on the digit line satisfies a threshold after applying the first voltage, wherein coupling the boost component to the digit line is based at least in part on determining that the magnitude of the signal satisfies the threshold.
4. The method of claim 1 , further comprising:
determining that a duration of the write operation satisfies a threshold, wherein coupling the boost component to the digit line is based at least in part on determining that the duration satisfies the threshold.
5. The method of claim 1 , further comprising:
writing a logic state to the memory cell based at least in part on boosting the digit line to the second voltage using the boost component.
6. The method of claim 1 , wherein the first voltage applied to the digit line is a first value or a second value based at least in part on a logic state being written to the memory cell during the write operation.
7. The method of claim 6 , further comprising:
applying a third voltage to a plate line coupled with the memory cell that is different than the first voltage applied to the digit line.
8. The method of claim 1 , further comprising:
isolating the digit line from a sense component after coupling the boost component with the digit line, wherein boosting the digit line to the second voltage is based at least in part on isolating the digit line from the sense component.
9. The method of claim 8 , further comprising:
recoupling the digit line with the sense component after boosting the digit line to the second voltage; and
applying a third voltage to the digit line after recoupling the digit line with the sense component.
10. The method of claim 9 , wherein a magnitude of the third voltage applied to the digit line is equal to a magnitude of a voltage applied to a plate line coupled with the memory cell during the write operation.
11. The method of claim 1 , wherein the boost component includes at least a portion of a second memory cell coupled with the digit line.
12. The method of claim 1 , wherein the memory cell and the boost component each comprise at least one ferroelectric capacitor.
13. A method comprising:
applying, during a write operation, a voltage to a digit line coupled with a memory cell; and
transferring a charge onto the digit line from an energy storage component after applying the voltage.
14. The method of claim 13 , further comprising:
determining that a magnitude of a signal on the digit line during the write operation satisfies a threshold, wherein transferring the charge onto the digit line from the energy storage component is based at least in part on determining that the magnitude of the signal satisfies the threshold.
15. The method of claim 13 , further comprising:
determining that a duration of the write operation satisfies a threshold, wherein transferring the charge onto the digit line from the energy storage component is based at least in part on determining that the duration satisfies the threshold.
16. The method of claim 13 , further comprising:
writing a logic state to the memory cell based at least in part on transferring the charge onto the digit line from the energy storage component.
17. The method of claim 13 , wherein the voltage applied to the digit line varies based at least in part on a logic state being written to the memory cell during the write operation.
18. The method of claim 13 , further comprising:
isolating the digit line from a sense component before transferring the charge onto the digit line from the energy storage component; and
recoupling the digit line with the sense component after transferring the charge onto the digit line from the energy storage component.
19. The method of claim 18 , further comprising:
applying a second voltage to the digit line after recoupling the digit line with the sense component, wherein a magnitude of the second voltage is equal to a magnitude of a third voltage applied to a plate line coupled with the memory cell during the write operation.
20. An electronic memory apparatus, comprising:
a memory cell;
a boost component; and
a controller coupled with the memory cell and the boost component, wherein the controller is operable to:
applying, during a write operation, a first voltage to a digit line coupled with the memory cell;
coupling the boost component to the digit line during the write operation based at least in part on applying the first voltage; and
boosting the digit line to a second voltage during the write operation based at least in part on coupling the boost component to the digit line.