Method of storing and retrieving data for a resistive random access memory (RRAM) array with multi-memory cells per bit
View Patent ↗Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
1. A method of storing and retrieving data for a resistive random access memory array, comprising:
subdividing the resistive random access memory array into a plurality of memory bits, with each memory bit comprising more than two memory cells;
programming an individual memory bit by substantially simultaneously changing resistive states of the more than two memory cells within the individual memory bit; and
reading the individual memory bit by determining summed current through all memory cells within the individual memory bit, wherein each memory cell is uniquely addressed by the combination of a wordline and a bitline, and wherein all the memory cells in a memory bit are addressed by paired wordlines and an individual bitline.
2. The method of claim 1 wherein the memory cells of the individual memory bit are read simultaneously.
3. The method of claim 1 wherein the memory cells of the individual memory bit are read non-simultaneously.
4. The method of claim 1 wherein the resistive random access memory array comprises phase change memory.
5. The method of claim 1 wherein the resistive random access memory array comprises multivalent metal oxide.
6. The method of claim 1 wherein the resistive random access memory array comprises conductive bridging random access memory.
7. The method of claim 1 wherein the resistive random access memory array comprises binary oxide.
8. A method of storing and retrieving data for a resistive random access memory array, comprising:
subdividing the resistive random access memory array into a plurality of memory bits, with each memory bit comprising at least two memory cells;
programming an individual memory bit by substantially simultaneously changing resistive states of the at least two memory cells within the individual memory bit; and
reading the individual memory bit by determining summed current through all memory cells within the individual memory bit, wherein each memory cell is uniquely addressed by the combination of a wordline and a bit line, and wherein all the memory cells in a memory bit are addressed by paired bitlines and an individual wordline.
9. The method of claim 8 wherein the resistive random access memory array comprises phase change memory.
10. The method of claim 8 wherein the resistive random access memory array comprises multivalent metal oxide.
11. The method of claim 8 wherein the resistive random access memory array comprises conductive bridging random access memory.
12. The method of claim 8 wherein the resistive random access memory array comprises binary oxide.
13. The method of claim 8 wherein the memory cells of the individual memory bit are read simultaneously.
14. The method of claim 8 wherein the memory cells of the individual memory bit are read non-simultaneously.
15. A method of storing and retrieving data for a resistive random access memory array, comprising:
subdividing the resistive random access memory array into a plurality of memory bits, each memory bit comprising a set of at least two coupled memory cells with all memory bits in the array having equivalent sets;
programming a memory bit by substantially simultaneously changing resistive states of all the coupled memory cells within the set, each individual memory bit being configured to be separately programmed relative to other of the memory bits, the programming of each memory bit including addressing the set of coupled memory cells by paired wordlines and a single bitline or by paired bitlines and a single wordline; and
reading the memory bit by determining summed current through all memory cells within the memory bit.
16. The method of claim 15 wherein each set contains exactly two memory cells.
17. The method of claim 16 wherein the coupled memory cells of each of the individual memory bits are addressed by paired wordlines and individual bitlines.
18. The method of claim 16 wherein the coupled memory cells of each of the individual memory bits are addressed by paired bitlines and individual wordlines.
19. The method of claim 15 wherein the resistive random access memory array comprises phase change memory.
20. The method of claim 15 wherein the resistive random access memory array comprises multivalent metal oxide.
21. The method of claim 15 wherein the resistive random access memory array comprises conductive bridging random access memory.