Apparatuses and methods for latching data input bits

1. An apparatus comprising:

a plurality of input buffers, each configured to receive multiple data bits in a serial data stream;

a first circuit including a first input coupled to a first input buffer of the plurality of input buffers and further including a second input coupled to a second input buffer of the plurality of input buffers, the first circuit is configured to receive a DQS signal and to latch a first data bit of the multiple data bits selected from the first input buffer or the second input buffer responsive to the DQS signal; and

a second circuit including a first input coupled to the first input buffer and further including a second input coupled to the second input buffer, the second circuit is configured to receive the DQS signal and to latch a second data bit of the multiple data bits selected from the first input buffer or the second input buffer responsive to the DQS signal;

wherein the first circuit is configured to latch the first data bit responsive to a first clock edge of the DQS signal and the second circuit is configured to latch the second data bit responsive to a second clock edge of the DQS signal opposite in direction to the first clock edge.

2. The apparatus of claim 1 further comprising:

a third circuit including a first input coupled to a third input buffer of the plurality of input buffers and further including a second input coupled to a fourth input buffer of the plurality of input buffers, the third circuit is configured to receive the DQS signal and to latch a third data bit of the multiple data bits selected from the third input buffer or the fourth input buffer responsive to the DQS signal; and

a fourth circuit including a first input coupled to the third input buffer and further including a second input coupled to the fourth input buffer, the third circuit is configured to receive the DQS signal and to latch a fourth data bit of the multiple data bits selected from the third input buffer or the fourth input buffer responsive to the DQS signal.

3. The apparatus of claim 2 , wherein the third circuit is configured to latch the third data bit responsive to the first clock edge of the DQS signal and the fourth circuit is configured to latch the fourth data bit responsive to the second clock edge of the DQS signal.

4. The apparatus of claim 1 , wherein, responsive to an even/odd switching signal:

the first circuit is configured to latch the first data bit selected from the first input buffer and the second circuit is configured to latch the second data bit selected from the second input buffer: or

the first circuit is configured to latch the first data bit selected from the second input buffer and the second circuit is configured to latch the second data bit selected from the first input buffer.

5. The apparatus of claim 1 , wherein the first circuit comprises:

a first sub-circuit configured to receive a first plurality of data bits of the multiple data bits from the first input buffer and configured to latch the first plurality of data bits from the first input buffer responsive to the DQS signal;

a second sub-circuit configured to receive a second plurality of data bits of the multiple data bits from the second input buffer and configured to latch the second plurality of data bits from the second input buffer responsive to the DQS signal; and

a selection circuit coupled to the first sub-circuit and the second sub-circuit and configured to select an output from one of the first sub-circuit and the second sub-circuit responsive to an even/odd switching signal that is provided based on the DQS signal.

6. The apparatus of claim 5 , wherein the DQS signal comprises a plurality of even DQS signals and a plurality of odd DQS signals, one of the plurality of even DQS signals and the plurality of odd DQS signals are set active during an initialization of the apparatus, and wherein:

when the plurality of even DQS signals are active, the selection circuit is configured to select the output from the first sub-circuit; and

when the plurality of odd DQS signals are set active, the selection circuit is configured to select the output from the second sub-circuit.

7. The apparatus of claim 6 , wherein the first sub-circuit comprises:

a first set of latches configured to receive the first plurality of data bits from the first input buffer, each of the first set of latches is configured to latch one of the first plurality of data bits from the first input buffer responsive to a corresponding even DQS signal in the plurality of even DQS signals; and

a second set of latches configured to latch simultaneously the first plurality of data bits from the first set of latches responsive to a last even DQS signal in the plurality of even DQS signals.

8. The apparatus of claim 7 , wherein the second sub-circuit comprises:

a third set of latches configured to receive the second plurality of data bits from the second input buffer, each of the third set of latches is configured to latch one of the second plurality of data bits from the second input buffer responsive to a corresponding odd DQS signal in the plurality of odd DQS signals; and

a fourth set of latches configured to latch simultaneously the second plurality of data bits from the third set of latches responsive to a last odd DQS signal in the plurality of odd DQS signals.

9. The apparatus of claim 8 , wherein the first circuit further comprises:

a fifth set of latches configured to latch the output from the selection circuit responsive to the last even DQS signal or the last odd DQS signal;

wherein:

the second set of latches in the first sub-circuit are configured to latch the first plurality of data bits from the first set of latches responsive to the last even DQS signal; and

the fourth set of latches in the second sub-circuit are configured to latch the second plurality of data bits from the third set of latches responsive to the last odd DQS signal.

10. The apparatus of claim 6 , wherein:

each even DQS signal in the plurality of even DQS signals is delayed in sequence from a preceding even DQS signal by a delay time between two succeeding data bits in the first input buffer; and

each odd DQS signal in the plurality of odd DQS signals is delayed in sequence from a preceding odd DQS signal by the delay time between the two succeeding data bits in the first input buffer.

11. The apparatus of claim 2 , wherein the third circuit comprises:

a first sub-circuit configured to receive a third plurality of data bits of the multiple data bits from the third input buffer and configured to latch the third plurality of data bits from the third input buffer responsive to the DQS signal;

a second sub-circuit configured to receive a fourth plurality of data bits of the multiple data bits from the fourth input buffer and configured to latch the fourth plurality of data bits from the fourth input buffer responsive to the DQS signal; and

a selection circuit coupled to the first sub-circuit and the second sub-circuit and configured to select output from one of the first sub-circuit and the third sub-circuit responsive to an even/odd switching signal that is provided based on the DQS signal.

12. The apparatus of claim 11 , wherein the DQS signal comprises a plurality of even DQS signals and a plurality of odd DQS signals, one of the plurality of even DQS signals and the plurality of odd DQS signals are set active during an initialization of the apparatus, and wherein:

when the plurality of even DQS signals are active, the selection circuit is configured to select the output from the first sub-circuit; and

when the plurality of odd DQS signals are active, the selection circuit is configured to select the output from the second sub-circuit.

13. The apparatus of claim 6 , wherein the second circuit comprises:

a multiplexer including a first input coupled to the first input buffer and further including a second input coupled to the second input buffer, the multiplexer is configured to select data bits from one of the first input buffer and the second input buffer responsive to the even/odd switching signal.

14. The apparatus of claim 13 , wherein:

when the plurality of even DQS signals are active, the multiplexer circuit is configured to select the data bits from the second input buffer; and

when the plurality of odd DQS signals are active, the selection circuit is configured to select the data bits from the first input buffer.

15. The apparatus of claim 12 , wherein the fourth circuit comprises:

a multiplexer including a first input coupled to the third input buffer and further including a second input coupled to the fourth input buffer, the multiplexer is configured to select data bits from one of the third input buffer and the fourth input buffer responsive to the even/odd switching signal.

16. The apparatus of claim 15 , wherein:

when the plurality of even DQS signals are active, the multiplexer circuit is configured to select the data bits from the fourth input buffer; and

when the plurality of odd DQS signals are active, the selection circuit is configured to select the output from the third input buffer.