Electronic device with a timing adjustment mechanism

1. An electronic device, comprising:

a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal;

a decision circuit coupled to the variable delay circuit, the decision circuit configured to:

generate a start signal for the variable delay circuit to begin measuring a coarse delay,

generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and

generate an inversion-decision signal based at least in part on measuring the coarse delay; and

an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to:

receive a clock input, and

based on the inversion-decision signal, control a phase for the clock input in generating the variable delay input.

2. The electronic device of claim 1 , wherein the input selection circuit is configured to send into the variable delay circuit the variable delay input that is either synchronized with the clock input or phase-shifted 180° from the clock input.

3. The electronic device of claim 1 , wherein the input selection circuit includes an inverting mechanism configured to send either a start-enabled signal or an inverted signal as the variable delay input, wherein the start-enabled signal is synchronized with the clock input and the inverted signal is an inverted form of the clock input corresponding to the 180° phase shift.

4. The electronic device of claim 3 , wherein the inverting mechanism is a multiplexer configured to:

receive the start-enabled signal and the inverted form of the start-enabled signal as the inverted signal;

receive the inversion-decision signal; and

send either the start-enabled signal or the inverted signal according to the inversion-decision signal.

5. The electronic device of claim 2 , further comprising:

an input buffer coupled to the input selection circuit and the decision circuit, the input buffer configured to generate a clock reference signal based on an input signal received from a source outside of a delayed locked loop (DLL), wherein the clock reference signal is an input to the input selection circuit;

wherein the decision circuit includes:

a trim circuit coupled to the input buffer, the trim circuit configured to generate a trimmed reference signal based on trimming the clock reference signal.

6. The electronic device of claim 1 , wherein the decision circuit includes:

a first circuit coupled to the trim circuit, the first circuit configured to generate a synced-internal stop synchronized with the clock reference signal; and

a second circuit coupled to the trim circuit, the second circuit configured to generate an inverted-internal stop that is phase offset 180° from the clock reference signal.

7. The electronic device of claim 6 , wherein:

the first circuit includes, a first multiplexer and a first latch configured to generate the synced-internal stop based on a rising edge of the clock reference signal; and

the second circuit includes, a second multiplexer and a second latch configured to generate the inverted-internal stop based on a falling edge of the clock reference signal.

8. The electronic device of claim 7 , wherein the decision circuit further includes a stop generator coupled to the first circuit and the second circuit, the stop generator configured to generate the stop signal according to either the synced-internal stop or the inverted-internal stop that arrives first at a stop decision mechanism.

9. The electronic device of claim 8 , wherein the stop decision mechanism is an OR gate.

10. The electronic device of claim 7 , wherein the decision circuit further includes an inversion-decision circuit comprising:

a decision timing circuit coupled to the first circuit and the second circuit, the decision timing circuit configured to sample and resynchronize the inverted-internal stop; and

an inversion decision mechanism coupled to the decision timing circuit, the inversion decision mechanism configured to generate the inversion-decision signal based on an output of the decision timing circuit.

11. The electronic device of claim 10 , wherein the decision timing circuit is configured to:

generate a first internal output based on sampling the inverted-internal stop at a rising edge of the synced-internal stop; and

generate a second internal output based on synchronizing the first internal output with the clock reference signal.

12. The electronic device of claim 11 , wherein the decision timing circuit includes:

a first flip-flop configured to generate the first internal output; and

a second flip-flop configured to generate the second internal output.

13. The electronic device of claim 10 , further comprising:

an initialization logic configured to generate a measure signal representing a duration of measurement phase; and

wherein:

the inversion decision mechanism is configured to generate the inversion-decision signal based an output of the decision timing circuit, wherein the output is released when measurement is done.

14. The electronic device of claim 13 , wherein the inversion decision mechanism includes an AND gate configured to generate the inversion-decision signal based on the measure signal and the output of the decision timing circuit.

15. The electronic device of claim 6 , wherein:

the trim circuit is further configured to generate a trimmed feedback signal based on trimming a model delayed signal; and

the decision circuit includes a start generator configured to generate the start signal based on the trimmed feedback signal.

16. The electronic device of claim 15 , wherein the start generator includes a start latch and a start buffer.

17. The electronic device of claim 15 , wherein the start generator corresponds to a coarse delay that matches a strobe duration associated with the stop signal.

18. The electronic device of claim 15 , the electronic device comprising a dynamic random-access memory (DRAM).

19. A delay locked loop (DLL) initialization circuit, comprising:

an input selection circuit configured to generate a signal that either matches an input signal or is an inverse thereof;

a variable delay line coupled to the input selection circuit, the variable delay line configured to add a variable amount of delay to the signal from the input selection circuit; and

a decision circuit coupled to the input selection circuit and the variable delay line, the decision circuit configured to:

generate a start signal and a stop signal based on the input signal and a feedback of a processing result of the input signal, and

generate an inversion-decision signal based on the input signal for controlling a phase of the signal from the input selection circuit,

wherein:

the start signal and the stop signal are for measuring a coarse delay,

the inversion-decision signal controls operation of the input selection circuit,

the coarse delay and the inversion-decision signal provide an initial timing for the DLL.

20. The DLL initialization circuit of claim 19 , wherein the input selection circuit includes a selection multiplexer configured to select either a start-enabled signal or an inverted signal to generate the signal, wherein the start-enabled signal is synchronized with the input signal and the inverted signal is an inverted form of the input signal.

21. The DLL initialization circuit of claim 19 , wherein the decision circuit includes:

a first circuit configured to generate a synced-internal stop based on a rising edge of the clock reference signal following the start signal;

a second circuit configured to generate an inverted-internal stop based on a falling edge of the clock reference signal following the start signal;

an OR gate configured to generate the stop signal according to either the synced-internal stop or the inverted-internal stop that arrives first at the OR gate;

a set of flip-flops configured to sample the inverted-internal stop at a rising edge of the synced-internal stop and synchronize a sampled value with the clock reference signal; and

an AND gate configured to generate the inversion-decision signal according to on an output of the set of flip-flops and measure signal.

22. A method of operating an electronic device, the method comprising:

generating a clock reference signal based on an input clock signal from a source outside of a delay locked loop (DLL);

generating a start signal based on a model delayed signal resulting from allowing the clock reference signal to initially travel through the electronic device or a portion thereof;

generating a stop signal based on a transition in the clock reference signal that occurs after generating the start signal;

measuring a coarse code between the start signal and the stop signal, wherein the coarse code represents an offset duration between transitions in the clock reference signal for generating an output signal; and

generating an inversion-decision signal according to a direction of the transition in the clock reference signal used to generate the stop signal, wherein the inversion-decision signal is for controlling a phase shift of the clock reference signal for generating the output signal.

23. The method of claim 22 , further comprising generating the output signal from the input clock signal for the DLL according to the coarse code and the inversion-decision signal.

24. The method of claim 23 , wherein generating the output signal includes:

selecting, according to the inversion-decision signal, either a signal synchronized with the clock reference signal or an inverted form of the clock reference signal; and

delaying the selected signal according to the coarse code.

25. The method of claim 22 , wherein generating the stop signal includes, after generating the start signal:

generating a synced-internal stop based on a rising edge of the clock reference signal;

generating an inverted-internal stop based on a falling edge of the clock reference signal; and

generating the stop signal based on either the synced-internal stop or the inverted-internal stop that occurs first.

26. The method of claim 25 , wherein generating the inversion-decision signal includes:

sampling the inverted-internal stop at a rising edge of the synced-internal stop; and

resynchronizing a result of the sampling with the clock reference signal.