IP Library Patent Application 16103994
Patent Application
App. No. 16/103,994

METHOD AND SYSTEM FOR INPUT/OUTPUT PROCESSING FOR WRITE THROUGH TO ENABLE HARDWARE ACCELERATION

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Quick Facts
Patent No.
US None
App. No.
16/103,994
Abstract

A system and method for efficient write through processing of Input/Output (I/O) requests are provided. One example of the illustrative method includes receiving a first write request to a first row, while processing the first write request, receiving a subsequent write request to the first row, and then caching the subsequent write request for processing until the first write request is completed.

Claims (47)

1 . A method for processing Input/Output (I/O) requests, the method comprising:

receiving a first write request to a first row;

while processing the first write request, receiving a subsequent write request to the first row; and

caching the subsequent write request for processing until the first write request is completed.

2 . The method of claim 1 , further comprising:

while processing the first write requesting, receiving a read request to the first row; and

processing the read request in parallel with processing the first write request.

3 . The method of claim 1 , wherein the first write request is received from a first host and wherein the subsequent write request is received from a second host that is different from the first host.

4 . The method of claim 1 , further comprising:

coalescing all write requests received from a host until processing of the first write request is completed; and

after processing of the first write request is completed, enabling further processing of all write requests that were coalesced during processing of the first write request.

5 . The method of claim 1 , further comprising:

determining that the first write request has completed processing; and

after determining that the first write request has completed processing, enabling the subsequent write request to be processed.

6 . The method of claim 1 , further comprising:

while processing the first write request, receiving a second subsequent write request;

determining that the second subsequent write request is to a second row that is different from the first row; and

enabling the second subsequent write request to be processed in parallel with processing the first write request.

7 . The method of claim 1 , further comprising:

updating a parity drive in connection with processing the first write request.

8 . The method of claim 1 , further comprising:

allocating cache memory in response to receiving the first write request; and

utilizing the allocated cache memory in connection with caching the subsequent write request.

9 . A memory control system, comprising:

a host interface that receives one or more host Input/Output (I/O) requests;

a storage interface that enables communication with a plurality of storage devices configured in a storage array;

a microprocessor; and

memory that includes computer-readable instructions that are executable by the microprocessor, the instructions enabling performance of a write through process and including:

instructions that receive a first write request to a first row;

instructions that, while processing the first write request, receive a subsequent write request to the first row; and

instructions that cache the subsequent write request for processing until the first write request is completed.

10 . The memory control system of claim 9 , wherein the instructions further include instructions that, while processing the first write requesting, receive a read request to the first row as well as instructions that process the read request in parallel with processing the first write request.

11 . The memory control system of claim 9 , wherein the first write request is received from a first host and wherein the subsequent write request is received from a second host that is different from the first host.

12 . The memory control system of claim 9 , wherein the instructions further include instructions that coalesce all write requests received from a host until processing of the first write request is completed after processing of the first write request is completed, enable further processing of all write requests that were coalesced during processing of the first write request.

13 . The memory control system of claim 9 , wherein the instructions further include instructions that determine that the first write request has completed processing and after determining that the first write request has completed processing, enable the subsequent write request to be processed.

14 . The memory control system of claim 9 , wherein the instructions further include instructions that, while processing the first write request, receive a second subsequent write request, determine that the second subsequent write request is to a second row that is different from the first row, and enable the second subsequent write request to be processed in parallel with processing the first write request.

15 . The memory control system of claim 9 , wherein the instructions further include instructions that update a parity drive in connection with processing the first write request.

16 . The memory control system of claim 9 , wherein the instructions further include instructions that allocate cache memory in response to receiving the first write request and utilize the allocated cache memory in connection with caching the subsequent write request.

17 . A cache system, comprising:

cache memory; and

instructions that enable management of the cache memory to facilitate a write through to be performed, the instructions including:

instructions that receive a first write request to a first row;

instructions that, while processing the first write request, receive a subsequent write request to the first row; and

instructions that cache the subsequent write request for processing until the first write request is completed.

18 . The cache system of claim 17 , wherein the instructions further include instructions that, while processing the first write requesting, receive a read request to the first row as well as instructions that process the read request in parallel with processing the first write request.

19 . The cache system of claim 17 , wherein the instructions further include instructions that coalesce all write requests received from a host until processing of the first write request is completed after processing of the first write request is completed, enable further processing of all write requests that were coalesced during processing of the first write request.

20 . The cache system of claim 17 , wherein the instructions further include instructions that, while processing the first write request, receive a second subsequent write request, determine that the second subsequent write request is to a second row that is different from the first row, and enable the second subsequent write request to be processed in parallel with processing the first write request.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE OF THE MERGER AND APPLICATION NOS. 13/237,550 AND 16/103,107 FROM THE MERGER PREVIOUSLY RECORDED ON REEL 047231 FRAME 0369. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048549/0113 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047231/0369 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2018
From: SIMIONESCU, HORIA; HOGLUND, TIMOTHY; VEERLA, SRIDHAR RAO; PANDIT, PANTHINI; RADHAKRISHNAN, GOWRISANKAR
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 046728/0001 →