Apparatuses and methods for command signal delay
View Patent ↗Apparatuses and methods for a command decoder delay are disclosed. An example apparatus includes a command decoder which may receive memory access command. The command decoder may provide an output command based on the memory access command to a command path at a first time. The command decoder may also provide the output command to a data path at a second time, wherein the second time is delayed relative to the first time.
1. An apparatus comprising:
a command decoder configured to receive memory access command, the command decoder configured to provide an output command based on the memory access command to a command path at a first time, the command decoder further configured to provide the output command to a data path at a second time, wherein the second time is delayed relative to the first time, wherein the command decoder is configured to delay provision of the output command to the data path until the second time based on a column access strobe (CAS) latency.
2. The apparatus of claim 1 , wherein the command decoder is configured to delay provision of the output command to the data path until the second time further based on a propagation delay of the data path.
3. The apparatus of claim 2 , wherein the command decoder comprises a command shift circuit configured to receive the output command at the first time, the CAS latency, and a count value, wherein the count value is based on the propagation delay of the data path, wherein the command shift circuit is configured to delay provision of the output signal to the data path to the second time based on a difference between the CAS latency and the count value.
4. The apparatus of claim 3 , further comprising a count detect circuit configured to model the propagation delay of the data path to determine the count value.
5. An apparatus comprising:
a command decoder configured to receive memory access command, the command decoder configured to provide an output command based on the memory access command to a command path at a first time, the command decoder further configured to provide the output command to a data path at a second time, wherein the second time is delayed relative to the first time, wherein the command path comprises a command extension circuit configured to receive the output signal at the first time; and provide the output signal at a third time after a command delay, wherein the command delay is based on the CAS latency.
6. The apparatus of claim 5 , further comprising an output circuit coupled to the data path and to the command path, wherein the output circuit is configured to receive data at the second time and provide the data in response to the third signal at the third time.
7. The apparatus of claim 6 , wherein the output circuit includes a FIFO circuit.
8. A method comprising:
receiving a memory access command at a command decoder of a memory;
providing an output command to a command path at a first time;
providing the output command to a data path at a second time, wherein the second time is delayed relative to the first time;
receiving output data at an output circuit at a third time based on propagation delay of the data path; and
outputting the output data from the output circuit at a fourth time based on a column access strobe latency from receipt of the memory access command at the command decoder.
9. A method comprising:
receiving a memory access command at a command decoder of a memory;
providing an output command to a command path at a first time;
providing the output command to a data path at a second time, wherein the second time is delayed relative to the first time; and
configuring the relative delay between the first time and the second time based on a propagation delay of the data path.
10. The method of claim 9 , further comprising modeling the propagation delay of the data path to determine the relative delay between the first time and the second time.
11. The method of claim 10 , wherein the configuring the delay comprises subtracting the modeled propagation delay from a column access strobe (CAS) latency.
12. The method of claim 11 , wherein the configuring the delay further comprises subtracting additional time from the CAS latency to provide a timing margin.
13. An apparatus comprising:
a data path circuit that includes memory components that are configured to retrieve data in response to a command signal received at a first time and configured to provide the data and an input signal at a second time;
a command path circuit that includes a command extension circuit configured to, in response to the command signal received at a third time, provide an output signal at a fourth time, wherein the first time is after the third time and the fourth time is after the second time; and
an output circuit configured to store the data at the second time in response to the input signal and provide the stored data to an output at the fourth time in response to the output signal; and
a command decoder circuit configured to receive a command signal and to provide the command signal to the command path at the third time and to selectively provide the command signal to the data path at the first time.
14. The memory of claim 13 , wherein the command decoder circuit comprises a command shift circuit configured to selectively delay the first time relative to the third time.
15. The apparatus of claim 14 , wherein the delay between the third time and the first time is based, at least in part, on the modeled difference between the first time and the second time.
16. The apparatus of claim 15 , wherein the command shift circuit is coupled to a count detect circuit configured to provide a model of the difference between the first time and the second time.
17. The apparatus of claim 15 , wherein the count detect circuit comprises models configured to model latency characteristics at least some of the memory components.
18. The apparatus of claim 13 , wherein the fourth time is a margin number of clock cycles from the third time.