Three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple

1. A method for fabricating a semiconductor device, comprising:

forming a bottom tier comprising a plurality of first vertical transistors and at least one contact formed on a first inverter gate;

forming a top tier comprising a plurality of second vertical transistors and a second inverter gate; and

connecting the bottom tier to the top tier to create a three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple by forming a monolithic inter-tier via (MIV) that lands on the at least one contact via the second inverter gate, and forming a ground contact from the top tier to a bottom source/drain region of the bottom tier.

2. The method of claim 1 , wherein at least one of the first and second vertical transistors comprises a vertical transport field-effect transistor (VTFET).

3. The method of claim 1 , wherein the plurality of first vertical transistors is associated with a first conductivity type and the plurality of second vertical transistors is associated with a second conductivity type.

4. The method of claim 3 , wherein the first conductivity type is n-type and the second conductivity type is p-type.

5. The method of claim 1 , wherein the vertical transistor device comprises a six-transistor memory cell.

6. The method of claim 5 , Therein the bottom tier comprises two vertical transistors and the top tier comprises four vertical transistors.

7. The method of claim 1 , wherein forming the top tier further comprises transferring, on the bottom tier, a layer of semiconductor material for forming the top tier using wafer bonding.

8. The method of claim 7 , wherein the wafer bonding comprises oxide-oxide wafer bonding.

9. A method for fabricating a semiconductor device, comprising:

forming a bottom tier comprising a plurality of first vertical transport field-effect transistors (VTFETs) associated with a first conductivity type and at least one contact formed on a first inverter gate;

forming a top tier comprising a plurality of second VTFETs associated with a second conductivity type and a second inverter gate; and

connecting the bottom tier to the top tier to create a three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple by forming a monolithic inter-tier via (MIV) that lands on the at least one contact via the second inverter gate, and forming a ground contact from the top tier to a bottom source/drain region of the bottom tier.

10. The method of claim 9 , wherein the first conductivity type is n-type and the second conductivity type is p-type.

11. The method of claim 9 , wherein the vertical transistor device comprises a six-transistor memory cell.

12. The method of claim 11 , wherein the bottom tier comprises two vertical transistors and the top tier comprises four vertical transistors.

13. The method of claim 9 , wherein forming the top tier further comprises transferring, on the bottom tier, a layer of semiconductor material for forming the top tier using wafer bonding.

14. The method of claim 13 , wherein the wafer bonding comprises oxide-oxide wafer bonding.

15. A semiconductor device comprising:

a bottom tier comprising a plurality of first vertical transistors and at least one contact disposed on a first inverter gate;

a top tier comprising a plurality of second vertical transistors and a second inverter gate;

a monolithic inter-tier via (MIV) that lands on the at least one contact via the second inverter gate; and

a ground contact connecting the top tier to a bottom source/drain region of the bottom tier;

the MIV and the ground contact forming a three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple.

16. The device of claim 15 , wherein at least one of the first and second vertical transistor devices comprises a vertical transport field-effect transistor (VTFET).

17. The device of claim 15 , wherein the plurality of first vertical transistors is associated with a first conductivity type and the plurality of second vertical transistors is associated with a second conductivity type.

18. The device of claim 17 , wherein the first conductivity type is n-type and the second conductivity type is p-type.